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Mobile World Congress – Barcelona, Spain

Live 4K demo of VESA Display Stream Compression (DSC)

February 27-March 2, 2017

Hall 7 Stand 7H40

Hardent Announces Availability of New Xilinx Versal ACAP Training Courses

New Xilinx Versal ACAP training courses will cover all aspects of designing with the latest Xilinx device category.

Hardent Announces Expansion of Xilinx Training in the USA

Hardent selected by Xilinx to be the new Xilinx training provider in four U.S. states.

Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies

PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.

Upcoming Sessions

Jan 26–28

Designing with the Zynq UltraScale+ RFSoC

Jan 26–28

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Jan 27–28

Designing with Versal AI Engine 2

Feb 01–04

Introduction to UVM

Complete Course Schedule

Simon Robin

President

Linked-in

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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