Live Online Webinar | System Protection for Zynq UltraScale+ MPSoCs

System Protection Features of Zynq UltraScale+ MPSoCs

Presenter: Troy Jones
This webinar will highlight the different system protection features of Xilinx Zynq UltraScale+ MPSoCs, including ARM TrustZone technology, the XMPU, XPPU, and SMMU.

14:00 EST

~~Register Now~~

This webinar is now over, but you can register here to watch a recorded version of the webinar.

Hardent & Xilinx Collaborate to Deliver Complete 8K Ready DisplayPort 1.4 IP Subsystem

New IP solution combining Hardent and Xilinx IP will enable pro A/V designers to take advantage of the full DisplayPort 1.4 feature set to support resolutions up to 8K.

FPGA Design Analysis Using the Vivado Design Suite

Useful commands for FPGA design analysis in the Vivado Design Suite that will help you save time and meet your performance goals!

Hardent & WHDL Named PSS Training Provider For Breker Trek5 Tool Suite

New PSS training course from Hardent and WHDL will cover unique Breker Trek5 UVM/SoC deployment and modeling capabilities.

Upcoming Sessions

Sep 24–26

Embedded System Design for the Zynq UltraScale+ MPSoC

Sep 24–25

Designing FPGAs Using the Vivado Design Suite 1

Oct 03–04

Designing with the Zynq UltraScale+ RFSoC

Oct 07–10

Introduction to Universal Verification Methodology (UVM)

Complete Course Schedule

Simon Robin

President

Linked-in

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

First Name

Last Name

Title

Company

Phone

City

Country

Subject

Tick to hear more from Hardent by email. This includes our newsletter, details about offers, new courses, and events. You can opt out at any time. For further information, please refer to our privacy policy.