Join us at DVCon 2016 in San Jose to find out how a web-based platform can be used to automate register verification and documentation for today’s complex FPGA designs.
For design and functional verification engineers, producing an error-free, reusable, and testable design can be a time-consuming task. IP reuse and integration in chip design is growing in complexity, making it more difficult to rely upon manual functional verification processes. As such, new methodologies need to be developed in order to assist development teams with producing a quality design on time and on budget.
One approach to reduce the cost and time associated with this increasingly complex process is to automate the register verification and documentation generation of chip and IP. In collaboration with ADVA Optical Networking, we have developed a client-server method that enables the automation of this process.
Our method, named ‘Hdocx’, uses a web interface, database, and Python scripting to enable developers in chip and IP design. Using hierarchical combinations of registers and documents, a chip-level document, RTL, and verification code outputs are created. ‘Hdocx’ automates the creation of the chip register map, register testing, chip decode logic, and firmware/chip integration. By automating the register and documentation functions, human errors can be detected early in the design process, while developing documentation is simplified and consistent from project to project.
‘Hdocx’ provides an easy to use interface for the following aspects of chip design.
- Creating reusable hierarchical chip and IP definitions for registers, memory, interrupt registers
- Creating hierarchical design, verification, and test outputs based on chip and IP definition files
- Creating reusable hierarchical documentation based on the chip and IP definition files and supporting design documentation
- Creating HTML formatted register maps and chip and IP descriptions that are available via URL address
The ‘Hdocx’ method will be presented March 1, 2016 at DVCon in San Jose by Scott Orangio (ADVA) and Julien Gagnon (Hardent). A poster and paper will describe in more detail how a web-based client/server model can be used to create, modify, reuse, and integrate IP register and documentation into a complete chip design.
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