• About Us
    • History
    • Mission
    • Team
    • Partners & Memberships
    • Customer Stories
  • Applications
    • Video
    • Automotive
    • Aerospace & Defense
    • Industrial
    • Telecommunications
  • News
    • Press Releases
    • Blog
    • Events
  • Careers
  • Contact
  • LinkedIn
  • Twitter
  • Engineering
    • FPGA & ASIC Design
    • FPGA & ASIC Verification
    • ASIC Prototyping
    • Digital Signal Processing
    • Embedded Software Design
    • Electronic System-Level Design
    • Power / Signal Integrity Analysis
    • System & Hardware Architecture
  • IP Products
    • Why Choose Hardent IP Products?
    • VESA DSC IP Cores
    • VDC-M IP Cores
    • DisplayPort 1.4 IP Subsystem
    • HDMI 2.1 IP Cores
    • ECC/Reed-Solomon FEC IP Cores
    • Mathematically Lossless Video Compression IP Cores
  • Training
    • Training Schedule
    • Training Courses
      • Xilinx Training
      • Verification Training
      • Complete Course List
    • Training Formats
      • Classroom Training
      • Private Training
      • Live Online Training
      • On-Demand Training
Back to
News from Hardent

Hardent to Showcase VESA DSC Demonstration on 4K Display at MIPI DevCon

September 8, 2016

First live 4K display demo of the visually lossless VESA DSC standard will show how higher resolution displays for mobile and mobile-influenced markets such as AR/VR can be effectively achieved.

Hardent, a MIPI® Alliance contributor member and provider of IP products, will showcase the first ever public demonstration of VESA Display Stream Compression with a 4K display at the MIPI Alliance’s inaugural developers conference, taking place September 14-15, 2016, at the Computer History Museum in Mountain View, California. MIPI DevCon participants will have the opportunity to see firsthand how the DSC standard can be leveraged to develop higher resolution displays of 4K and beyond.

The VESA DSC standard was developed by the Video Electronics Standards Association (VESA) as an industry-wide compression standard for use in display applications where visually lossless, ultra-low latency compression is required. The DSC algorithm decreases transmission bandwidth by up to 3X, allowing designers to achieve higher resolution displays using existing transport interfaces, such as MIPI Display Serial Interface (DSI), while lowering power, overall system costs, and electromagnetic interference (EMI).

Hardent will be showcasing a 4K demonstration of VESA DSC in the exhibitor area throughout MIPI DevCon. A variety of DSC compressed and source images and videos will be shown live side-by-side to illustrate DSC’s visually lossless picture quality. “We are pleased to be launching our new 4K DSC demo at MIPI DevCon,” says Alain Legault, VP IP Products at Hardent. “By demonstrating DSC on a fully-scalable, modular development platform, we aim to show that the standard can be leveraged to create compelling displays for many different applications, each with their own unique transport and display requirements.”

To complement the demo, Hardent is also scheduled to give a presentation at MIPI DevCon entitled “How to use the VESA DSC standard to create higher resolution displays in consumer electronics applications”. The presentation will provide an overview of the DSC standard and discuss the benefits of implementing DSC in mobiles/tablets, in-car video applications, AR/VR headsets, 4K/8K/UHD TVs, digital signage, and computer displays.

To see a live 4K demo of VESA Display Stream Compression, visit Hardent’s exhibitor space at MIPI DevCon. For more information about VESA DSC, or to request a private demo, contact Hardent.

Hardent attending Mipi Devcon conference
Latest News
Contact Us
Hardent Announces Availability of New Xilinx Versal ACAP Training Courses
New Xilinx Versal ACAP training courses will cover all aspects of designing with the latest Xilinx device category.
More
Hardent Announces Expansion of Xilinx Training in the USA
Hardent selected by Xilinx to be the new Xilinx training provider in four U.S. states.
More
Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies
PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.
More
Upcoming Sessions
Jan 27–28
Designing with Versal AI Engine 2
Register
Feb 01–04
Introduction to UVM
Register
Feb 02–03
Designing with the Versal ACAP: Embedded Processor Architecture and Methodology
Register
Feb 03–04
Advanced Hardware Debugging Techniques Using Vivado Design Suite
Register
Complete Course Schedule
Contact Hardent
Simon Robin
President
Linked-in
HardentMontreal
450 rue Saint-Pierre, suite 300
Montreal
,
QC
H2Y 2M9
Canada
T +1 (514) 284-5252
F +1 (514) 284-5052
Tick to hear more from Hardent by email. This includes our newsletter, details about offers, new courses, and events. You can opt out at any time. For further information, please refer to our privacy policy.

We made the decision to work with Hardent as we felt confident that their strategic approach to the development process, combined with their technical expertise and training credentials, would help us to successfully reach our end goal and equip our in-house team with the electronic design knowledge to complete not just this project but other projects in the future.

Stefan Grigoras
Operations Manager
NDT Technologies Inc.
More testimonials
Partners & Memberships
Xilinx APC logo
mipi member logo
VESA
Hardent © 2002-2021.
All rights reserved.
  • Privacy Policy
We use cookies to ensure that we give you the best experience on our website. By continuing to use this website, you consent to our use of cookies. OK