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Advanced Hardware Debugging Techniques Using Vivado Design Suite

It looks like this training event has been changed. Please check our course schedule or contact training@hardent.com for more information.

Mary-Ann Conly

Training Coordinator

Wondering Which Course to Take?

Check out our full course list or download our learning path guide to find the right course level and topic for you!

Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

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Free Webinar

May 5 | 14:00 EST
Developing Algorithms for Versal ACAP: Optimization

Includes a live Q&A session with our trainer Reg Zatrepalek!

Upcoming Sessions

Rambus Completes Acquisition of Hardent

Strengthens CXL Memory Interconnect Initiative and accelerates roadmap of data center solutions

Rambus to Acquire Hardent, Accelerating Roadmap for Next-Generation Data Center Solutions

Augments world-class engineering team with deep SoC digital design expertise for Rambus CXL Memory Interconnect Initiative

Frame Buffer Compression IP Subsystem for TCON IC Manufacturers Launched by Hardent

Proven IP subsystem enables TCON IC manufacturers to leverage new Embedded DisplayPort low power features and significantly reduce frame buffer area using VESA DSC.

Upcoming Sessions

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Mary-Ann Conly

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HardentMontreal

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Stefan Grigoras

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NDT Technologies Inc.

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