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Advanced Hardware Debugging Techniques Using Vivado Design Suite

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Mary-Ann Conly

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$99 Versal ACAP Workshops

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September 23, Live Online
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September 28, Live Online
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September 29, Live Online
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Upcoming Sessions

Sep 20–22

Advanced VHDL for Verification

Sep 22

Introduction to Signal Integrity for Xilinx FPGAs

Sep 23

Workshop: Introduction to Versal ACAP Programmable Logic Architecture

Sep 27–29

Advanced Timing Closure Techniques for the Vivado Design Suite

Complete Course Schedule

Hardent VESA DSC and FEC IP Cores Licensed by Kinetic Technologies

Kinetic Technologies selects Hardent’s IP cores to create ultra-low power MST hub with VESA DSC support.

Hardent Joins Samsung SAFE™ IP Partner Program & Launches New Display IP Subsystem Solution in Collaboration with Rambus

New Rambus MIPI® DSI-2℠ / Hardent VESA® DSC host IP subsystem supports Samsung Foundry customers designing next-generation display products.

Hardent Selected as Design Services Provider for New Xilinx Kria SOMs

Hardent will support AI developers, embedded developers, and system architects to develop applications using the latest Xilinx device family.

Upcoming Sessions

Sep 20–22

Advanced VHDL for Verification

Sep 22

Introduction to Signal Integrity for Xilinx FPGAs

Sep 23

Workshop: Introduction to Versal ACAP Programmable Logic Architecture

Sep 27–29

Advanced Timing Closure Techniques for the Vivado Design Suite

Complete Course Schedule

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Mary-Ann Conly

Training Coordinator

HardentMontreal

450 rue Saint-Pierre, suite 300

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H2Y 2M9

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T +1 (514) 284-5252

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Sr. Director Global ASIC/FPGA/IP Development

ADVA Optical Networking

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