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Versal ACAP
Vitis Unified Software Platform
Vivado Design Suite / FPGA Design
DSP Design
Connectivity Design
Embedded System Design - Acceleration
Embedded System Design - Linux Development
Embedded System Design - Zynq-7000 SoC and Zynq US+ MPSoC
Functional Verification
HDL Design
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System Level Modeling and Verification
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Course List

Course Schedule

Course List

Whether you’re just starting out in your career, or you want to develop specialized skills, our course list has everything you need.

Wondering which course to take? Download our learning path to find the right course level and topic for the next step in your career development.

Programmable Logic Architecture for the Versal ACAPHardent Exclusive
Embedded Processor Architecture for the Versal ACAPHardent Exclusive
Designing with the Versal ACAP: Network on ChipNew
Designing with Versal AI Engine 1: Architecture and Design Flow
Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels
Designing with Versal AI Engine 3: Kernel Programming and OptimizationNew
Designing with the Versal ACAP: Power and Board DesignNew
Designing with the Versal ACAP: PCI Express SystemsNew

Vitis Unified Software Platform

High-Level Synthesis with the Vitis HLS ToolNew
Accelerating Applications with the Vitis Unified Software Environment
Developing AI Inference Solutions with the Vitis AI Platform
Migrating to the Vitis Embedded Software Development IDE Workshop

VIVADO DESIGN SUITE / FPGA DESIGN

FPGA Design with Vivado Design Suite: The EssentialsHardent Exclusive
Designing with the UltraScale and UltraScale+ Architectures
Improve Your Vivado Design Suite ProductivityHardent Exclusive
Vivado Design Suite Advanced XDC and Static Timing Analysis with Design MethodologyHardent Exclusive
Advanced Hardware Debugging Techniques Using Vivado Design SuiteHardent Exclusive
Designing with Dynamic Function eXchange (DFX) Using the Vivado Design SuiteNew
Advanced Timing Closure Techniques for the Vivado Design SuiteHardent Exclusive

High-Level Synthesis with the Vitis HLS ToolNew
DSP Primer
DSP Design Using System Generator

CONNECTIVITY DESIGN

Designing with the Zynq UltraScale+ RFSoC
Designing with Xilinx Serial Transceivers
Introduction to Signal Integrity for Xilinx FPGAs
Designing with Ethernet MAC Controllers

EMBEDDED SYSTEM DESIGN - ACCELERATION

Accelerating Applications with the Vitis Unified Software Environment

EMBEDDED SYSTEM DESIGN - LINUX DEVELOPMENT

Embedded Design with PetaLinux Tools

EMBEDDED SYSTEM DESIGN - ZYNQ-7000 SOC AND ZYNQ US+ MPSOC

Embedded System Design for the Zynq UltraScale+ MPSoCHardent Exclusive
Embedded Systems Design
Embedded Systems Software Design

FUNCTIONAL VERIFICATION

SystemVerilog for VerificationHot Topic
SystemVerilog Assertions
Introduction to UVMHot Topic
Advanced UVM
SystemVerilog for Verification (On-Demand)Start Now!
SystemVerilog Assertions (On-Demand)Start Now!
Introduction to UVM (On-Demand)Start Now!

Designing with VHDLHot Topic
SystemVerilog for Design
Verilog for Design
Verilog Fundamentals for SystemVerilog

PROGRAMMING LANGUAGES

Introduction to Perl
Introduction to TCL-tk
Essential Tcl Scripting for the Vivado Design Suite

System Level Modeling and Verification

Introduction to C++ for Modeling
SystemC Introduction for Modeling with TLM 2.0
TLM 2.0

Webinar: How to Use the Versal ACAP Programmable Network on Chip (NoC)New
Webinar: Algorithm Acceleration Using Xilinx Platforms (REL)
Webinar: Debugging Tips for the Vivado Design Suite (REL)
Webinar: Error Injection Strategies for UVM-Based Verification (REL)
Webinar: An Introduction to the UVM Register Layer (REL)

Mary-Ann Conly

Training Coordinator

Training Webinars

July 13
Constraints Management for Vivado
Register Now

August 4
Get Ready to Use Vitis
Register Now

Webinars are free to attend and include a live Q&A with our trainers!

Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

Upcoming Sessions

Jun 22–23

Improve Your Vivado Design Suite Productivity

Jun 28–30

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Jun 28–29

High-Level Synthesis with the Vitis HLS Tool

Jun 29–30

Embedded Systems Software Design

Complete Course Schedule

Hardent VESA DSC and FEC IP Cores Licensed by Kinetic Technologies

Kinetic Technologies selects Hardent’s IP cores to create ultra-low power MST hub with VESA DSC support.

Hardent Joins Samsung SAFE™ IP Partner Program & Launches New Display IP Subsystem Solution in Collaboration with Rambus

New Rambus MIPI® DSI-2℠ / Hardent VESA® DSC host IP subsystem supports Samsung Foundry customers designing next-generation display products.

Hardent Selected as Design Services Provider for New Xilinx Kria SOMs

Hardent will support AI developers, embedded developers, and system architects to develop applications using the latest Xilinx device family.

Upcoming Sessions

Jun 22–23

Improve Your Vivado Design Suite Productivity

Jun 28–30

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Jun 28–29

High-Level Synthesis with the Vitis HLS Tool

Jun 29–30

Embedded Systems Software Design

Complete Course Schedule

Contact Hardent

Mary-Ann Conly

Training Coordinator

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

,

QC

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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In our case, they just log into our servers and we are in constant contact via IM, email, phone, etc., but they have all their own design tools as well, so they can work either way. Being in the same time zone makes working with them easy. I am sure you will be happy with the outcome of their work. They’ll hit the ground running much faster than a single contractor would.

Marshall Johnson

Sr. Director Global ASIC/FPGA/IP Development

ADVA Optical Networking

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