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Versal ACAP
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DSP Design
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Embedded System Design - Zynq-7000 SoC
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Course List

Course Schedule

Course List

Whether you’re just starting out in your career, or you want to develop specialized skills, our course list has everything you need.

Wondering which course to take? Download our learning path to find the right course level and topic for the next step in your career development.

Designing with the Versal ACAP: Architecture and MethodologyNew
Designing with the Versal ACAP: Programmable Logic Architecture and MethodologyHardent Exclusive
Designing with the Versal ACAP: Embedded Processor Architecture and MethodologyHardent Exclusive
Designing with the Versal ACAP: Network on ChipNew
Designing with Versal AI Engine 1New
Designing with Versal AI Engine 2New

Vitis Unified Software Platform

Accelerating Applications with the Vitis Unified Software EnvironmentNew
Developing AI Inference Solutions with the Vitis AI PlatformNew
Migrating to the Vitis Embedded Software Development IDE WorkshopNew

VIVADO DESIGN SUITE / FPGA DESIGN

FPGA Design with Vivado Design Suite: The EssentialsHardent Exclusive
Designing with the UltraScale and UltraScale+ Architectures
Improve Your Vivado Design Suite ProductivityHardent Exclusive
Vivado Design Suite Advanced XDC and Static Timing Analysis with Design MethodologyHardent Exclusive
Advanced Hardware Debugging Techniques Using Vivado Design SuiteHardent Exclusive
Xilinx Partial Reconfiguration Tools and Techniques
Advanced Timing Closure Techniques for the Vivado Design SuiteHardent Exclusive

DSP Primer
C-based Design – High-Level Synthesis with the Vivado HLx ToolHot Topic
DSP Design Using System Generator

CONNECTIVITY DESIGN

Designing with the Zynq UltraScale+ RFSoC
Designing with Xilinx Serial Transceivers
Introduction to Signal Integrity for Xilinx FPGAs
Designing with Ethernet MAC Controllers

EMBEDDED SYSTEM DESIGN - ACCELERATION

Accelerating Applications with the Vitis Unified Software EnvironmentNew

EMBEDDED SYSTEM DESIGN - LINUX DEVELOPMENT

Embedded Design with PetaLinux Tools

EMBEDDED SYSTEM DESIGN - ZYNQ-7000 SoC

Embedded Systems Design
Embedded Systems Software Design
Introduction to the Zynq SoC Architecture
Zynq SoC System Architecture

EMBEDDED SYSTEM DESIGN - ZYNQ ULTRASCALE+ MPSOC

Embedded System Design for the Zynq UltraScale+ MPSoCHardent Exclusive
Zynq UltraScale+ MPSoC for the Hardware Designer
Zynq UltraScale+ MPSoC for the Software Developer
Zynq UltraScale+ MPSoC for the System Architect

FUNCTIONAL VERIFICATION

SystemVerilog for VerificationHot Topic
SystemVerilog Assertions
Introduction to UVMHot Topic
Advanced UVM
SystemVerilog for Verification (On-Demand)Start Now!
SystemVerilog Assertions (On-Demand)Start Now!
Introduction to UVM (On-Demand)Start Now!

Designing with VHDLHot Topic
SystemVerilog for Design
Verilog for Design
Verilog Fundamentals for SystemVerilog

PROGRAMMING LANGUAGES

Introduction to Perl
Introduction to TCL-tk
Essential Tcl Scripting for the Vivado Design Suite

System Level Modeling and Verification

Introduction to C++ for Modeling
SystemC Introduction for Modeling with TLM 2.0
TLM 2.0

VESA DISPLAY STREAM COMPRESSION

VESA Display Stream Compression (DSC) Primer

Webinar: Debugging Tips for the Vivado Design Suite (REL)New
Webinar: Get Ready to Use the Xilinx Vitis Platform (REL)New
Webinar: Error Injection Strategies for UVM-Based Verification (REL)
Webinar: An Introduction to the UVM Register Layer (REL)
Webinar: Getting Started With Xilinx Zynq UltraScale+ MPSoCs (REL)

Mary-Ann Conly

Training Coordinator

Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

See our list of resources

Upcoming Sessions

Jan 27–28

Designing with Versal AI Engine 2

Feb 01–04

Introduction to UVM

Feb 02–03

Designing with the Versal ACAP: Embedded Processor Architecture and Methodology

Feb 03–04

Advanced Hardware Debugging Techniques Using Vivado Design Suite

Complete Course Schedule

Hardent Announces Availability of New Xilinx Versal ACAP Training Courses

New Xilinx Versal ACAP training courses will cover all aspects of designing with the latest Xilinx device category.

Hardent Announces Expansion of Xilinx Training in the USA

Hardent selected by Xilinx to be the new Xilinx training provider in four U.S. states.

Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies

PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.

Upcoming Sessions

Jan 27–28

Designing with Versal AI Engine 2

Feb 01–04

Introduction to UVM

Feb 02–03

Designing with the Versal ACAP: Embedded Processor Architecture and Methodology

Feb 03–04

Advanced Hardware Debugging Techniques Using Vivado Design Suite

Complete Course Schedule

Contact Hardent

Mary-Ann Conly

Training Coordinator

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

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QC

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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Operations Manager

NDT Technologies Inc.

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