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Course List

Course Schedule

Course List

Whether you’re just starting out in your career, or you want to develop specialized skills, our course list has everything you need.

Wondering which course to take? Download our learning path to find the right course level and topic for the next step in your career development.

Advanced Hardware Debugging Techniques Using Vivado Design Suite
Migrating to the Vitis Embedded Software Development IDE Workshop
Accelerating Applications with the Vitis Unified Software Environment
FPGA Design with Vivado Design Suite: The Essentials
Improve Your Vivado Design Suite Productivity
Advanced Timing Closure Techniques for the Vivado Design Suite

VIVADO DESIGN SUITE / FPGA DESIGN

FPGA Design with Vivado Design Suite: The EssentialsHardent Exclusive
Designing with the UltraScale and UltraScale+ Architectures
Improve Your Vivado Design Suite ProductivityHardent Exclusive
Vivado Design Suite Advanced XDC and Static Timing Analysis with Design MethodologyHardent Exclusive
Advanced Hardware Debugging Techniques Using Vivado Design SuiteHardent Exclusive
Xilinx Partial Reconfiguration Tools and Techniques
Advanced Timing Closure Techniques for the Vivado Design SuiteHardent Exclusive

DSP Primer
C-based Design – High-Level Synthesis with the Vivado HLx ToolHot Topic
DSP Design Using System Generator

CONNECTIVITY DESIGN

Designing with the Zynq UltraScale+ RFSoC
Designing with Xilinx Serial Transceivers
Introduction to Signal Integrity for Xilinx FPGAs
How to Design a High-Speed Memory Interface
Designing with Ethernet MAC Controllers

EMBEDDED SYSTEM DESIGN - ACCELERATION

Accelerating Applications with the Vitis Unified Software EnvironmentNew

EMBEDDED SYSTEM DESIGN - LINUX DEVELOPMENT

Embedded Design with PetaLinux Tools

EMBEDDED SYSTEM DESIGN - ZYNQ-7000 SoC

Embedded Systems Design
Embedded Systems Software Design
Introduction to the Zynq SoC Architecture
Zynq SoC System Architecture

EMBEDDED SYSTEM DESIGN - ZYNQ ULTRASCALE+ MPSOC

Embedded System Design for the Zynq UltraScale+ MPSoCHardent Exclusive
Zynq UltraScale+ MPSoC for the Hardware Designer
Zynq UltraScale+ MPSoC for the Software Developer
Zynq UltraScale+ MPSoC for the System Architect

FUNCTIONAL VERIFICATION

SystemVerilog for VerificationHot Topic
SystemVerilog for Verification (On-Demand)Start Now!
SystemVerilog Assertions
Introduction to Universal Verification Methodology (UVM)Hot Topic
Introduction to UVM Universal Verification Methodology (On-Demand)Start Now!
Advanced Universal Verification Methodology (UVM)

Designing with VHDLHot Topic
SystemVerilog for Design
Verilog for Design
Verilog Fundamentals for SystemVerilog

PROGRAMMING LANGUAGES

Introduction to Perl
Introduction to TCL-tk
Essential Tcl Scripting for the Vivado Design Suite
Essential Tcl Scripting for the Vivado Design Suite (On-Demand)Start Now!

System Level Modeling and Verification

Introduction to C++ for Modeling
SystemC Introduction for Modeling with TLM 2.0
TLM 2.0

VESA DISPLAY STREAM COMPRESSION

VESA Display Stream Compression (DSC) Primer

Webinar: Debugging Tips for the Vivado Design SuiteNew
Webinar: Get Ready to Use the Xilinx Vitis Platform (REL)New
Webinar: Error Injection Strategies for UVM-Based Verification (REL)
Webinar: An Introduction to the UVM Register Layer (REL)
Webinar: Getting Started With Xilinx Zynq UltraScale+ MPSoCs (REL)

Mary-Ann Conly

Training Coordinator

November Webinar

November 23 @ 14:00 EST
Vivado Debugging Tips

Includes live demos and a Q&A session with our trainer!

Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

See our list of resources

Upcoming Sessions

Oct 26–29

Introduction to Universal Verification Methodology (UVM)

Oct 28–29

Designing with Xilinx Serial Transceivers

Nov 02–05

SystemVerilog for Verification

Nov 04–05

Advanced Hardware Debugging Techniques Using Vivado Design Suite

Complete Course Schedule

Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies

PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.

Hardent Becomes Authorized Microchip Design Partner

FPGA design services and support from Hardent will enable Microchip customers to get their products to market more quickly.

Hardent Joins Forces with Maojet & Fujisoft To Expand Presence in Asia

We recently appointed Maojet Technology Corporation as our new IP representative for Taiwan, and Fujisoft as our new IP representative for Japan. We will be working closely with both companies to develop our IP business within these two key markets.

Upcoming Sessions

Oct 26–29

Introduction to Universal Verification Methodology (UVM)

Oct 28–29

Designing with Xilinx Serial Transceivers

Nov 02–05

SystemVerilog for Verification

Nov 04–05

Advanced Hardware Debugging Techniques Using Vivado Design Suite

Complete Course Schedule

Contact Hardent

Mary-Ann Conly

Training Coordinator

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

,

QC

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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