| DATE | COURSE | LOCATION | STATUS | SHARE |
| May 28, 2019 | PCIe Protocol Overview | Live E-Learning | Register | |
| May 29–30, 2019 | Designing an Integrated PCI Express System | Live E-Learning | Register | |
| May 30–31, 2019 | Designing with the Zynq UltraScale+ RFSoC | Montreal, QC |
Register Confirmed
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| Jun 03–06, 2019 | Introduction to Universal Verification Methodology (UVM) | Orlando, FL | Register | |
| Jun 03–06, 2019 | SystemVerilog for Verification | Live E-Learning | Register | |
| Jun 10–13, 2019 | SystemVerilog for Verification | Coquitlam, BC | Register | |
| Jun 10–13, 2019 | SystemVerilog for Verification | Burlington, MA | Register | |
| Jun 11–13, 2019 | Designing with VHDL | Live E-Learning |
Register Confirmed
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| Jun 14, 2019 | Advanced Features and Techniques of Embedded Systems Software Design | Live E-Learning | Register | |
| Jun 17–18, 2019 | Advanced Timing Closure Techniques for the Vivado Design Suite | Live E-Learning | Register |
Course Schedule