Electronic Design: Xilinx & Verification Training Courses

Xilinx & Functional Verification Training

Learn from industry experts with real-world engineering experience

Course Schedule

DATE	COURSE	LOCATION	STATUS	SHARE
Sep 24–27, 2018	Introduction to Universal Verification Methodology (UVM)	Live E-Learning	Register Confirmed	Share
Sep 26–27, 2018	Embedded Systems Software Design	Live E-Learning	Register Confirmed	Share
Oct 08–10, 2018	Embedded System Design for the Zynq UltraScale+ MPSoC	Orlando, FL	Register	Share
Oct 10–12, 2018	Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology	Live E-Learning	Register	Share
Oct 11–12, 2018	Embedded Design with PetaLinux Tools	Orlando, FL	Register	Share
Oct 15–16, 2018	C-based Design - High-Level Synthesis with the Vivado HLx Tool	Coquitlam, BC	Register	Share
Oct 15–18, 2018	Introduction to Universal Verification Methodology (UVM)	Coquitlam, BC	Register	Share
Oct 15–18, 2018	SystemVerilog for Verification	Live E-Learning	Register	Share
Oct 15–18, 2018	Introduction to Universal Verification Methodology (UVM)	San Jose, CA	Register	Share
Oct 16–18, 2018	Advanced Universal Verification Methodology (UVM)	Burlington, MA	Register	Share

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New VDC-M (VESA Display Compression-M) IP Cores

VDC-M encoder and decoder IP cores will support the new VESA Display Compression-M standard for mobile devices requiring increased video compression levels of up to 5X.

New On-Demand SystemVerilog for Verification Training Course

Training is a valuable tool for engineering teams wanting to increase productivity, but sometimes there is simply not enough time or money available to travel to a classroom location. Hardent’s new on-demand SystemVerilog for Verification training course bridges this gap and provides students all-around flexibility in learning to use SystemVerilog technology in their verification process.

Hardent IP Portfolio Supports New Features of HDMI 2.1 Specification

VESA DSC and Reed-Solomon FEC IP cores enable HDMI controller manufacturers and IP providers to quickly implement new features of HDMI 2.1 and support higher resolution displays.

Upcoming Sessions

Sep 24–27

Introduction to Universal Verification Methodology (UVM)

Sep 26–27

Embedded Systems Software Design

Oct 08–10

Embedded System Design for the Zynq UltraScale+ MPSoC

Oct 10–12

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Complete Course Schedule

Contact Hardent

Mary-Ann Conly

Training Coordinator

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

,

QC

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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