| DATE | COURSE | LOCATION | STATUS | SHARE |
| Jul 27–28, 2020 | Improve Your Vivado Design Suite Productivity | Live E-Learning | Register | |
| Jul 27–28, 2020 | Embedded Systems Software Design | Live E-Learning | Register | |
| Jul 29–30, 2020 | Accelerating Applications with the Vitis Unified Software Environment | Live E-Learning | Register | |
| Aug 04–06, 2020 | Designing with VHDL | Live E-Learning |
Register Confirmed
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| Aug 04–06, 2020 | SystemVerilog for Design | Live E-Learning | Register | |
| Aug 05–06, 2020 | Designing with the UltraScale and UltraScale+ Architectures | Live E-Learning | Register | |
| Aug 10–13, 2020 | SystemVerilog for Verification | Live E-Learning | Register | |
| Aug 11–12, 2020 | Designing with Ethernet MAC Controllers | Live E-Learning | Register | |
| Aug 11–13, 2020 | Advanced Timing Closure Techniques for the Vivado Design Suite | Live E-Learning | Register | |
| Aug 13, 2020 | SystemVerilog Assertions | Live E-Learning | Register |
Course Schedule