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Xilinx & Verification Training Courses
Quality training delivered by industry experts
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Course Schedule
Course List
DATE COURSE LOCATION STATUS SHARE
Mar 15–18, 2021 Introduction to UVM Live E-Learning Register
Confirmed
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Mar 16–18, 2021 Embedded System Design for the Zynq UltraScale+ MPSoC Live E-Learning Register
Confirmed
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Mar 17–18, 2021 Xilinx Partial Reconfiguration Tools and Techniques Live E-Learning Register
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Mar 22–23, 2021 High-Level Synthesis with the Vitis HLS Tool Live E-Learning Register
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Mar 22–23, 2021 FPGA Design with Vivado Design Suite: The Essentials Live E-Learning Register
Confirmed
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Mar 22–23, 2021 Designing with the Versal ACAP: Programmable Logic Architecture and Methodology Live E-Learning Register
Confirmed
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Mar 23–25, 2021 Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology Live E-Learning Register
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Mar 23–25, 2021 Designing with the Zynq UltraScale+ RFSoC Live E-Learning Register
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Mar 24–25, 2021 Designing with Versal AI Engine 1 Live E-Learning Register
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Mar 29–30, 2021 Designing with the Versal ACAP: Embedded Processor Architecture and Methodology Live E-Learning Register
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Showing results 1 to 10 of 73
Contact HardentContact me
Mary-Ann Conly
Training Coordinator
Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

New Courses

Versal ACAP: Programmable Logic Architecture & Methodology

Versal ACAP: Embedded Processor Architecture & Methodology

Versal ACAP: Network on Chip

Designing with the Versal AI Engine 1 

Designing with the Versal AI Engine 2

High-Level Synthesis (HLS) with Vitis

Accelerating Applications with Vitis

Vitis AI Platform

Migrating to the Vitis IDE

Advanced Hardware Debugging for Vivado

Advanced Timing Closure for Vivado

See all Courses
Latest News
Contact Us
Hardent Announces Availability of New Xilinx Versal ACAP Training Courses
New Xilinx Versal ACAP training courses will cover all aspects of designing with the latest Xilinx device category.
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Hardent Announces Expansion of Xilinx Training in the USA
Hardent selected by Xilinx to be the new Xilinx training provider in four U.S. states.
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Hardent and PLC2 Announce New IP Partnership to Support German Semiconductor Companies
PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.
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Upcoming Sessions
Mar 15–18
Introduction to UVM
Register
Mar 16–18
Embedded System Design for the Zynq UltraScale+ MPSoC
Register
Mar 17–18
Xilinx Partial Reconfiguration Tools and Techniques
Register
Mar 22–23
Designing with the Versal ACAP: Programmable Logic Architecture and Methodology
Register
Complete Course Schedule
Contact Hardent
Mary-Ann Conly
Training Coordinator
HardentMontreal
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Montreal
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QC
H2Y 2M9
Canada
T +1 (514) 284-5252
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Time to market was one of our first considerations in choosing Hardent to design a PCI communication bridge. They grasped the project requirements in a matter of days. Their impressive expertise and responsiveness made the development process very smooth, as if they were working right down the hall.

Nicolas Gonthier
Hardware Design Manager
Verint Systems Canada Inc.
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