Electronic Design: Xilinx & Verification Training Courses

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Spartan-6 Migration
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Vitis Unified Software Platform
Vivado Design Suite / FPGA Design
DSP Design
Connectivity Design
Embedded System Design - Acceleration
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Embedded System Design - Zynq-7000 SoC and Zynq US+ MPSoC
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There are currently no courses scheduled that match your criteria. We’d love to help though, so please get in touch with our training team.

Mary-Ann Conly

Training Coordinator

Hardent Exclusive Training Courses

Our exclusive courses have been developed by our very own team of in-house Xilinx and FPGA specialists.

Programmable Logic Architecture for the Versal ACAP

Embedded Processor Architecture for the Versal ACAP

Embedded System Design for the Zynq UltraScale+ MPSoC

FPGA Design with Vivado Design Suite: The Essentials 1

FPGA Design with Vivado Design Suite: The Essentials 2

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Advanced Timing Closure Techniques for the Vivado Design Suite

Advanced Hardware Debugging Techniques Using Vivado Design Suite

Migrating from Spartan-6

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Wondering Which Course to Take?

Check out our full course list or download our learning path guide to find the right course level and topic for you!

Rambus Completes Acquisition of Hardent

Strengthens CXL Memory Interconnect Initiative and accelerates roadmap of data center solutions

Rambus to Acquire Hardent, Accelerating Roadmap for Next-Generation Data Center Solutions

Augments world-class engineering team with deep SoC digital design expertise for Rambus CXL Memory Interconnect Initiative

Frame Buffer Compression IP Subsystem for TCON IC Manufacturers Launched by Hardent

Proven IP subsystem enables TCON IC manufacturers to leverage new Embedded DisplayPort low power features and significantly reduce frame buffer area using VESA DSC.

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Mary-Ann Conly

Training Coordinator

HardentMontreal

450 rue Saint-Pierre, suite 300

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H2Y 2M9

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T +1 (514) 284-5252

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