Electronic Design: Xilinx & Verification Training Courses

Xilinx & Functional Verification Training

Learn from industry experts with real-world engineering experience

Course Schedule

DATE	COURSE	LOCATION	STATUS	SHARE
Oct 23–25, 2018	Verilog for Design	Burlington, MA	Register Confirmed	Share
Oct 29–30, 2018	C-based Design - High-Level Synthesis with the Vivado HLx Tool	Ottawa, ON	Register	Share
Oct 30–Nov 01, 2018	Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology	Live E-Learning	Register	Share
Oct 30–Nov 01, 2018	Embedded System Design for the Zynq UltraScale+ MPSoC	Live E-Learning	Register	Share
Nov 05–07, 2018	Embedded System Design for the Zynq UltraScale+ MPSoC	Coquitlam, BC	Register	Share
Nov 05–08, 2018	SystemVerilog for Verification	Portland , OR	Register	Share
Nov 05–08, 2018	SystemVerilog for Verification	Toronto, ON	Register	Share
Nov 08–09, 2018	Embedded Design with PetaLinux Tools	Coquitlam, BC	Register	Share
Nov 13–16, 2018	SystemVerilog for Verification	Burlington, MA	Register	Share
Nov 13–16, 2018	SystemVerilog for Verification	Live E-Learning	Register	Share

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New VDC-M (VESA Display Compression-M) IP Cores

VDC-M encoder and decoder IP cores will support the new VESA Display Compression-M standard for mobile devices requiring increased video compression levels of up to 5X.

New On-Demand SystemVerilog for Verification Training Course

Training is a valuable tool for engineering teams wanting to increase productivity, but sometimes there is simply not enough time or money available to travel to a classroom location. Hardent’s new on-demand SystemVerilog for Verification training course bridges this gap and provides students all-around flexibility in learning to use SystemVerilog technology in their verification process.

Hardent IP Portfolio Supports New Features of HDMI 2.1 Specification

VESA DSC and Reed-Solomon FEC IP cores enable HDMI controller manufacturers and IP providers to quickly implement new features of HDMI 2.1 and support higher resolution displays.

Upcoming Sessions

Oct 23–25

Verilog for Design

Oct 29–30

C-based Design - High-Level Synthesis with the Vivado HLx Tool

Oct 30–Nov 01

Embedded System Design for the Zynq UltraScale+ MPSoC

Oct 30–Nov 01

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Complete Course Schedule

Contact Hardent

Mary-Ann Conly

Training Coordinator

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

,

QC

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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