| DATE | COURSE | LOCATION | STATUS | SHARE |
| Apr 07–08, 2020 | C-based Design - High-Level Synthesis with the Vivado HLx Tool | Live E-Learning |
Register Confirmed
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| Apr 13–16, 2020 | Introduction to Universal Verification Methodology (UVM) | Live E-Learning |
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| Apr 14–16, 2020 | FPGA Design with Vivado Design Suite: The Essentials | Live E-Learning |
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| Apr 15–16, 2020 | Designing with the UltraScale and UltraScale+ Architectures | Live E-Learning | Register | |
| Apr 21–23, 2020 | Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology | Live E-Learning |
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| Apr 27–29, 2020 | Embedded System Design for the Zynq UltraScale+ MPSoC | Live E-Learning |
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| Apr 27–30, 2020 | SystemVerilog for Verification | Live E-Learning |
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| Apr 28–29, 2020 | Embedded Design with PetaLinux Tools | Live E-Learning | Register | |
| Apr 30, 2020 | SystemVerilog Assertions | Live E-Learning |
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| May 05–07, 2020 | Designing with VHDL | Live E-Learning | Register |
Course Schedule