Electronic Design: Xilinx & Verification Training Courses

DATE	COURSE	LOCATION	STATUS	SHARE
Apr 26–29, 2021	Introduction to UVM	Live E-Learning	Register Confirmed	Share
Apr 27–28, 2021	Designing with Xilinx Serial Transceivers	Live E-Learning	Register Confirmed	Share
May 03–04, 2021	Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels	Live E-Learning	Register	Share
May 05–06, 2021	Designing with the Versal ACAP: Embedded Processor Architecture and Methodology	Live E-Learning	Register Confirmed	Share
May 10–11, 2021	High-Level Synthesis with the Vitis HLS Tool	Live E-Learning	Register Confirmed	Share
May 11–13, 2021	Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology	Live E-Learning	Register Confirmed	Share
May 12, 2021	Migrating to the Vitis Embedded Software Development IDE Workshop	Live E-Learning	Register	Share
May 12–13, 2021	Designing with Versal AI Engine 3: Kernel Programming and Optimization	Live E-Learning	Register	Share
May 17–18, 2021	Designing with the Versal ACAP: Programmable Logic Architecture and Methodology	Live E-Learning	Register	Share
May 17–19, 2021	Embedded System Design for the Zynq UltraScale+ MPSoC	Live E-Learning	Register	Share

Showing results 1 to 10 of 66