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Xilinx & Verification Training Courses
Quality training delivered by industry experts
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Course Schedule
Course List
DATE COURSE LOCATION STATUS SHARE
Apr 26–29, 2021 Introduction to UVM Live E-Learning Register
Confirmed
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Apr 27–28, 2021 Designing with Xilinx Serial Transceivers Live E-Learning Register
Confirmed
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May 03–04, 2021 Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels Live E-Learning Register
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May 05–06, 2021 Designing with the Versal ACAP: Embedded Processor Architecture and Methodology Live E-Learning Register
Confirmed
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May 10–11, 2021 High-Level Synthesis with the Vitis HLS Tool Live E-Learning Register
Confirmed
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May 11–13, 2021 Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology Live E-Learning Register
Confirmed
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May 12, 2021 Migrating to the Vitis Embedded Software Development IDE Workshop Live E-Learning Register
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May 12–13, 2021 Designing with Versal AI Engine 3: Kernel Programming and Optimization Live E-Learning Register
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May 17–18, 2021 Designing with the Versal ACAP: Programmable Logic Architecture and Methodology Live E-Learning Register
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May 17–19, 2021 Embedded System Design for the Zynq UltraScale+ MPSoC Live E-Learning Register
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Mary-Ann Conly
Training Coordinator
Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

New Versal ACAP Training Courses

Versal ACAP: Programmable Logic Architecture & Methodology

Versal ACAP: Embedded Processor Architecture & Methodology

Versal ACAP: Power & Board Design

Versal ACAP: Network on Chip

Designing with the Versal AI Engine 1 

Designing with the Versal AI Engine 2

Designing with the Versal AI Engine 3

See all Courses
New Vitis Training Courses

High-Level Synthesis (HLS) with Vitis

Accelerating Applications with Vitis

Vitis AI Platform

Migrating to the Vitis IDE

See all Courses
Latest News
Contact Us
Mixel, Rambus and Hardent Collaborate to Deliver State-of-the-Art Integrated MIPI Display Subsystem Solution
Mixel, Rambus and Hardent collaborate to offer a complete display IP subsystem solution.
More
Hardent Announces Availability of New Xilinx Versal ACAP Training Courses
New Xilinx Versal ACAP training courses will cover all aspects of designing with the latest Xilinx device category.
More
Hardent Announces Expansion of Xilinx Training in the USA
Hardent selected by Xilinx to be the new Xilinx training provider in four U.S. states.
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Upcoming Sessions
Apr 26–29
Introduction to UVM
Register
Apr 27–28
Designing with Xilinx Serial Transceivers
Register
May 03–04
Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels
Register
May 05–06
Designing with the Versal ACAP: Embedded Processor Architecture and Methodology
Register
Complete Course Schedule
Contact Hardent
Mary-Ann Conly
Training Coordinator
HardentMontreal
450 rue Saint-Pierre, suite 300
Montreal
,
QC
H2Y 2M9
Canada
T +1 (514) 284-5252
F +1 (514) 284-5052
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We made the decision to work with Hardent as we felt confident that their strategic approach to the development process, combined with their technical expertise and training credentials, would help us to successfully reach our end goal and equip our in-house team with the electronic design knowledge to complete not just this project but other projects in the future.

Stefan Grigoras
Operations Manager
NDT Technologies Inc.
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