Electronic Design: Xilinx & Verification Training Courses

DATE	COURSE	LOCATION	STATUS	SHARE
Mar 09–10, 2020	C-based Design - High-Level Synthesis with the Vivado HLx Tool	Ottawa, ON	Register	Share
Mar 10–11, 2020	Embedded Design with PetaLinux Tools	Live E-Learning	Register	Share
Mar 10–11, 2020	Accelerating Applications with the Vitis Unified Software Environment	Montreal, QC	Register Confirmed	Share
Mar 10–12, 2020	Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology	Coquitlam, BC	Register	Share
Mar 10–12, 2020	Designing with the Zynq UltraScale+ RFSoC	Toronto, ON	Register	Share
Mar 10–12, 2020	Advanced Timing Closure Techniques for the Vivado Design Suite	Live E-Learning	Register	Share
Mar 16–17, 2020	Designing FPGAs Using the Vivado Design Suite 1	Live E-Learning	Register	Share
Mar 16–19, 2020	SystemVerilog for Verification	Huntsville, AL	Register	Share
Mar 17–19, 2020	Verilog for Design	Live E-Learning	Register	Share
Mar 17–19, 2020	Advanced Timing Closure Techniques for the Vivado Design Suite	Raleigh, NC	Register	Share

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