Electronic Design: Xilinx & Verification Training Courses

Xilinx & Functional Verification Training

Learn from industry experts with real-world engineering experience

Course Schedule

DATE	COURSE	LOCATION	STATUS	SHARE
Mar 25–27, 2019	Embedded System Design for the Zynq UltraScale+ MPSoC	Live E-Learning	Register Confirmed	Share
Mar 25–28, 2019	Introduction to Universal Verification Methodology (UVM)	Live E-Learning	Register	Share
Mar 28, 2019	Verification Power User Breakfast	Toronto, ON	Register	Share
Apr 01–02, 2019	Zynq SoC System Architecture	Live E-Learning	Register	Share
Apr 02, 2019	FPGA Power User Breakfast	Orlando, FL	Register	Share
Apr 17, 2019	Advanced Features and Techniques of Embedded Systems Software Design	Live E-Learning	Register	Share
Apr 17–18, 2019	Designing FPGAs Using the Vivado Design Suite 1	Live E-Learning	Register Confirmed	Share
Apr 23–24, 2019	Designing with the Zynq UltraScale+ RFSoC	Ottawa, ON	Register	Share
Apr 23–24, 2019	Designing FPGAs Using the Vivado Design Suite 2	Live E-Learning	Register Confirmed	Share
Apr 24–25, 2019	Accelerating C, C++, OpenCL, and RTL Applications with the SDAccel Environment	Burlington, MA	Register	Share

Showing results 1 to 10 of 95

Hardent and Xilinx Collaborate to Deliver Complete 8K Ready DisplayPort 1.4 IP Subsystem

New IP solution combining Hardent and Xilinx IP will enable pro A/V designers to take advantage of the full DisplayPort 1.4 feature set to support resolutions up to 8K.

FPGA Design Analysis Using the Vivado Design Suite

Useful commands for FPGA design analysis in the Vivado Design Suite that will help you save time and meet your performance goals!

Hardent & Willamette HDL Named by Breker Verification Systems As PSS Training Provider For Trek5 Tool Suite

New PSS training course from Hardent and WHDL will cover unique Breker Trek5 UVM/SoC deployment and modeling capabilities.

Upcoming Sessions

Mar 25–28

Introduction to Universal Verification Methodology (UVM)

Mar 25–27

Embedded System Design for the Zynq UltraScale+ MPSoC

Mar 28

Verification Power User Breakfast

Apr 01–02

Zynq SoC System Architecture

Complete Course Schedule

Contact Hardent

Mary-Ann Conly

Training Coordinator

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

,

QC

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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