Electronic Design: Xilinx & Verification Training Courses

DATE	COURSE	LOCATION	STATUS	SHARE
Dec 13–14, 2021	Embedded Design with PetaLinux Tools	Live E-Learning	Register	Share
Dec 15–16, 2021	High-Level Synthesis with the Vitis HLS Tool	Live E-Learning	Register Confirmed	Share
Dec 16, 2021	Migrating from Spartan-6	Live E-Learning	Register Confirmed	Share
Dec 20–21, 2021	Designing with Versal AI Engine 2: Graph Programming with AI Engine Kernels	Live E-Learning	Register	Share
Dec 20–21, 2021	Designing with Xilinx Serial Transceivers	Live E-Learning	Register	Share
Jan 05–06, 2022	Designing with Versal AI Engine 3: Kernel Programming and Optimization	Live E-Learning	Register	Share
Jan 05–06, 2022	FPGA Design with Vivado Design Suite: The Essentials	Live E-Learning	Register	Share
Jan 10, 2022	Migrating from Spartan-6	Live E-Learning	Register	Share
Jan 10–13, 2022	Introduction to UVM	Live E-Learning	Register	Share
Jan 11–13, 2022	Advanced Timing Closure Techniques for the Vivado Design Suite	Live E-Learning	Register	Share

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