| DATE | COURSE | LOCATION | STATUS | SHARE |
| Jan 27–30, 2020 | SystemVerilog for Verification | Live E-Learning |
Register Confirmed
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| Jan 28–30, 2020 | Embedded System Design for the Zynq UltraScale+ MPSoC | Knoxville, TN |
Register Confirmed
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| Jan 30, 2020 | SystemVerilog Assertions | Live E-Learning |
Register Confirmed
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| Jan 31, 2020 | Debugging Techniques Using the Vivado Logic Analyzer | Knoxville, TN |
Register Confirmed
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| Feb 03–06, 2020 | Introduction to Universal Verification Methodology (UVM) | Coquitlam, BC | Register | |
| Feb 03–06, 2020 | SystemVerilog for Verification | Orlando, FL | Register | |
| Feb 10–13, 2020 | Introduction to Universal Verification Methodology (UVM) | Huntsville, AL | Register | |
| Feb 11–13, 2020 | Embedded System Design for the Zynq UltraScale+ MPSoC | Huntsville, AL | Register | |
| Feb 11–13, 2020 | Designing with the Zynq UltraScale+ RFSoC | North Reading, MA | Register | |
| Feb 11–13, 2020 | Advanced Timing Closure Techniques for the Vivado Design Suite | Orlando, FL | Register |
Course Schedule