Electronic Design: Xilinx & Verification Training Courses

DATE	COURSE	LOCATION	STATUS	SHARE
Dec 01–03, 2020	Advanced Timing Closure Techniques for the Vivado Design Suite	Live E-Learning	Register Confirmed	Share
Dec 08–10, 2020	Embedded System Design for the Zynq UltraScale+ MPSoC	Live E-Learning	Register Confirmed	Share
Dec 08–10, 2020	Advanced Universal Verification Methodology (UVM)	Live E-Learning	Register	Share
Dec 08–10, 2020	SystemVerilog for Design	Live E-Learning	Register	Share
Dec 14–15, 2020	Advanced Hardware Debugging Techniques Using Vivado Design Suite	Live E-Learning	Register	Share
Dec 15, 2020	Migrating to the Vitis Embedded Software Development IDE Workshop	Live E-Learning	Register Confirmed	Share
Dec 16–17, 2020	Accelerating Applications with the Vitis Unified Software Environment	Live E-Learning	Register	Share
Dec 16–17, 2020	Designing with the UltraScale and UltraScale+ Architectures	Live E-Learning	Register Confirmed	Share
Jan 12–13, 2021	Embedded Systems Software Design	Live E-Learning	Register	Share
Jan 12–13, 2021	C-based Design - High-Level Synthesis with the Vivado HLx Tool	Live E-Learning	Register	Share

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