| DATE | COURSE | LOCATION | STATUS | SHARE |
| Aug 09–11, 2021 | SystemVerilog for Design | Live E-Learning | Register | |
| Aug 10–11, 2021 | Designing with Versal AI Engine 3: Kernel Programming and Optimization | Live E-Learning | Register | |
| Aug 10–12, 2021 | Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology | Live E-Learning |
Register Confirmed
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| Aug 16–17, 2021 | High-Level Synthesis with the Vitis HLS Tool | Live E-Learning | Register | |
| Aug 16–18, 2021 | Advanced UVM | Live E-Learning |
Register Confirmed
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| Aug 17–18, 2021 | Advanced Hardware Debugging Techniques Using Vivado Design Suite | Live E-Learning | Register | |
| Aug 17–19, 2021 | Designing with VHDL | Live E-Learning | Register | |
| Aug 17–19, 2021 | Programmable Logic Architecture for the Versal ACAP | Live E-Learning | Register | |
| Aug 18–19, 2021 | Accelerating Applications with the Vitis Unified Software Environment | Live E-Learning | Register | |
| Aug 20, 2021 | Designing with the Versal ACAP: Network on Chip | Live E-Learning | Register |
Course Schedule