Electronic Design: Xilinx & Verification Training Courses

Xilinx & functional verification training

Taught by industry experts with real-world engineering experience

Course Schedule

DATE	COURSE	LOCATION	STATUS	SHARE
May 29–31, 2018	Embedded System Design for the Zynq UltraScale+ MPSoC	Live E-Learning	Register	Share
Jun 07–08, 2018	C-based Design - High-Level Synthesis with the Vivado HLx Tool	Live E-Learning	Register	Share
Jun 11–14, 2018	SystemVerilog for Verification	Live E-Learning	Register	Share
Jun 12–14, 2018	Embedded System Design for the Zynq UltraScale+ MPSoC	Ottawa, ON	Register	Share
Jun 12–14, 2018	Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology	Toronto, ON	Register	Share
Jun 20–22, 2018	Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology	Burlington, MA	Register	Share
Jun 26–28, 2018	Designing with VHDL	Live E-Learning	Register	Share
Jun 27–29, 2018	Embedded System Design for the Zynq UltraScale+ MPSoC	Burlington, MA	Register	Share
Jun 28, 2018	FPGA Power User Breakfast	Coquitlam, BC	Register	Share
Jul 10–12, 2018	Embedded System Design for the Zynq UltraScale+ MPSoC	Burlington, MA	Register	Share

Showing results 1 to 10 of 142

New VDC-M (VESA Display Compression-M) IP Cores

VDC-M encoder and decoder IP cores will support the new VESA Display Compression-M standard for mobile devices requiring increased video compression levels of up to 5X.

New On-Demand SystemVerilog for Verification Training Course

Training is a valuable tool for engineering teams wanting to increase productivity, but sometimes there is simply not enough time or money available to travel to a classroom location. Hardent’s new on-demand SystemVerilog for Verification training course bridges this gap and provides students all-around flexibility in learning to use SystemVerilog technology in their verification process.

Hardent IP Portfolio Supports New Features of HDMI 2.1 Specification

VESA DSC and Reed-Solomon FEC IP cores enable HDMI controller manufacturers and IP providers to quickly implement new features of HDMI 2.1 and support higher resolution displays.

Upcoming Sessions

Jun 11–14

SystemVerilog for Verification

Jun 20–22

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Jun 26–28

Designing with VHDL

Jun 27–29

Embedded System Design for the Zynq UltraScale+ MPSoC

Complete Course Schedule

Your first contact at Hardent for more information about our services

Contact Hardent

Mary-Ann Conly

Training Coordinator

HardentMontreal

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