| DATE | COURSE | LOCATION | STATUS | SHARE |
| Dec 17–19, 2019 | Designing with VHDL | Live E-Learning |
Register Confirmed
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| Jan 08–09, 2020 | Designing with the UltraScale and UltraScale+ Architectures | Live E-Learning | Register | |
| Jan 13–16, 2020 | SystemVerilog for Verification | Montreal, QC | Register | |
| Jan 13–16, 2020 | SystemVerilog for Verification | Huntsville, AL | Register | |
| Jan 14–15, 2020 | Embedded Design with PetaLinux Tools | Burlington, MA | Register | |
| Jan 14–15, 2020 | C-based Design - High-Level Synthesis with the Vivado HLx Tool | Live E-Learning | Register | |
| Jan 14–16, 2020 | Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology | Ottawa, ON | Register | |
| Jan 14–16, 2020 | Embedded System Design for the Zynq UltraScale+ MPSoC | Live E-Learning | Register | |
| Jan 14–16, 2020 | Advanced Timing Closure Techniques for the Vivado Design Suite | Coquitlam, BC | Register | |
| Jan 21–22, 2020 | C-based Design - High-Level Synthesis with the Vivado HLx Tool | Toronto, ON | Register |
Course Schedule