Electronic Design: Xilinx & Verification Training Courses

DATE	COURSE	LOCATION	STATUS	SHARE
Oct 26–29, 2020	Introduction to Universal Verification Methodology (UVM)	Live E-Learning	Register Confirmed	Share
Oct 28–29, 2020	Designing with Xilinx Serial Transceivers	Live E-Learning	Register Confirmed	Share
Nov 02–05, 2020	SystemVerilog for Verification	Live E-Learning	Register	Share
Nov 04–05, 2020	Advanced Hardware Debugging Techniques Using Vivado Design Suite	Live E-Learning	Register	Share
Nov 05, 2020	SystemVerilog Assertions	Live E-Learning	Register	Share
Nov 10–11, 2020	Embedded Design with PetaLinux Tools	Live E-Learning	Register	Share
Nov 10–11, 2020	C-based Design - High-Level Synthesis with the Vivado HLx Tool	Live E-Learning	Register	Share
Nov 10–12, 2020	Advanced Timing Closure Techniques for the Vivado Design Suite	Live E-Learning	Register	Share
Nov 16, 2020	Migrating to the Vitis Embedded Software Development IDE Workshop	Live E-Learning	Register	Share
Nov 16–17, 2020	Accelerating Applications with the Vitis Unified Software Environment	Live E-Learning	Register	Share

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