Electronic Design: Xilinx & Verification Training Courses

Xilinx & Functional Verification Training

Learn from industry experts with real-world engineering experience

Course Schedule

DATE	COURSE	LOCATION	STATUS	SHARE
Jan 23–25, 2019	Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology	Montreal, QC	Register Confirmed	Share
Jan 28–30, 2019	Embedded System Design for the Zynq UltraScale+ MPSoC	Orlando, FL	Register Confirmed	Share
Jan 28–31, 2019	SystemVerilog for Verification	Portland , OR	Register	Share
Jan 28–31, 2019	Introduction to Universal Verification Methodology (UVM)	Live E-Learning	Register Confirmed	Share
Jan 28–31, 2019	SystemVerilog for Verification	Toronto, ON	Register	Share
Jan 30–Feb 01, 2019	Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology	North Reading, MA	Register Confirmed	Share
Jan 31–Feb 01, 2019	Embedded Design with PetaLinux Tools	Orlando, FL	Register Confirmed	Share
Feb 04–05, 2019	C-based Design - High-Level Synthesis with the Vivado HLx Tool	Orlando, FL	Register	Share
Feb 04–05, 2019	Designing FPGAs Using the Vivado Design Suite 1	Live E-Learning	Register	Share
Feb 04–06, 2019	Embedded System Design for the Zynq UltraScale+ MPSoC	Live E-Learning	Register	Share

Showing results 1 to 10 of 112

Vivado Design Analysis for Performance

Useful commands for design analysis in the Vivado Design Suite that will help you save time and meet your performance goals! More and more FPGA designs these days have requirements that demand a wide and fast data processing pipeline. This is especially true with video pipelines processing streams of 8K at 120Hz or telecommunication applications […]

Hardent & Willamette HDL Named by Breker Verification Systems As Portable Test & Stimulus Standard (PSS) Training Provider For Trek5 Tool Suite

New PSS training course from Hardent and WHDL will cover unique Breker Trek5 UVM/SoC deployment and modeling capabilities.

Hardent and Willamette HDL Develop New Portable Test and Stimulus Standard Training Course

New PSS training course equips engineers using Cadence Perspec with the skills needed to accelerate SoC verification.

Upcoming Sessions

Jan 23–25

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Jan 28–30

Embedded System Design for the Zynq UltraScale+ MPSoC

Jan 28–31

SystemVerilog for Verification

Jan 28–31

Introduction to Universal Verification Methodology (UVM)

Complete Course Schedule

Contact Hardent

Mary-Ann Conly

Training Coordinator

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

,

QC

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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