| DATE | COURSE | LOCATION | STATUS | SHARE |
| Sep 24–25, 2019 | Designing FPGAs Using the Vivado Design Suite 1 | Live E-Learning |
Register Confirmed
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| Sep 24–26, 2019 | Embedded System Design for the Zynq UltraScale+ MPSoC | Montreal, QC |
Register Confirmed
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| Oct 03–04, 2019 | Designing with the Zynq UltraScale+ RFSoC | Huntsville, AL | Register | |
| Oct 07–10, 2019 | Introduction to Universal Verification Methodology (UVM) | Coquitlam, BC | Register | |
| Oct 07–10, 2019 | SystemVerilog for Verification | Montreal, QC | Register | |
| Oct 07–10, 2019 | Introduction to Universal Verification Methodology (UVM) | Live E-Learning | Register | |
| Oct 08–09, 2019 | Designing with the Zynq UltraScale+ RFSoC | Ottawa, ON | Register | |
| Oct 08–09, 2019 | Designing with the UltraScale and UltraScale+ Architectures | Live E-Learning | Register | |
| Oct 08–10, 2019 | Advanced Timing Closure Techniques for the Vivado Design Suite | Burlington, MA | Register | |
| Oct 08–10, 2019 | Designing with VHDL | Live E-Learning | Register |
Course Schedule