|On-Demand||Essential Tcl Scripting for the Vivado Design Suite (REL)||Recorded E-Learning||Register||Share||View Course Details|
|On-Demand||Essentials of 7 Series FPGAs (REL)||Recorded E-Learning||Register||Share||View Course Details|
|Oct 05–06, 2016||Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Design Suite Users (No Design Methodology)||Montreal, QC||Waiting List||Share||View Course Details|
|Oct 12–13, 2016||DSP Design Using System Generator||Burlington, MA||Register||Share||View Course Details|
|Oct 13–14, 2016||C-based Design - High-Level Synthesis with the Vivado HLx Tool||Live E-Learning||Register||Share||View Course Details|
|Oct 14, 2016||Essential Tcl Scripting for the Vivado Design Suite||Live E-Learning||Register||Share||View Course Details|
|Oct 17–18, 2016||Embedded Systems Design (Online)||Live E-Learning||Register||Share||View Course Details|
|Oct 18–20, 2016||ARM Cortex-M7 Software Development||Toronto, ON||Register||Share||View Course Details|
|Oct 19–21, 2016||Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Design Suite Users||Duluth, GA||Register||Share||View Course Details|
|Oct 25–27, 2016||Vivado Design Suite Static Timing Analysis and Design Constraints||Burlington, MA||Register||Share||View Course Details|
|Oct 26–27, 2016||Designing with the UltraScale Architecture||Live E-Learning||Register||Share||View Course Details|
|Oct 27, 2016||Vivado Design Suite for ISE Project Navigator Users||Live E-Learning||Register||Share||View Course Details|
|Oct 31–Nov 01, 2016||Essential DSP Implementation Techniques||Live E-Learning||Register||Share||View Course Details|
|Nov 02, 2016||Embedded C/C++ SDSoC Development Environment and Methodology (SDSoC license included)||Greensboro, NC||Register||Share||View Course Details|
|Nov 02–04, 2016||Designing with Verilog||Live E-Learning||Register||Share||View Course Details|
|Nov 02–04, 2016||Designing with Multi-Gigabit Serial I/O||Live E-Learning||Register||Share||View Course Details|
|Nov 07–10, 2016||Universal Verification Methodology (UVM)||Live E-Learning||Register||Share||View Course Details|
|Nov 07–10, 2016||Universal Verification Methodology (UVM)||Portland , OR||Register||Share||View Course Details|
|Nov 09, 2016||Essential Design with the PlanAhead Analysis and Design Tool||Live E-Learning||Register||Share||View Course Details|
|Nov 15–16, 2016||Zynq UltraScale+ MPSoC for the System Architect||Burlington, MA||Register||Share||View Course Details|
Your first contact at Hardent for more information about our services
Your first contact at Hardent for more information about our services:
Register now for one of our upcoming SDSoC training courses and get a node-locked SDSoC license* included.Hurry - offer available for a limited time only! * license valued at $995
Hardent offers technical training courses delivered in person and online. All of our trainers are experienced electronic design and software engineers with extensive hands-on experience in their training fields. As a Xilinx ATP and ARM ATC, we offer a wide range of training programs covering FPGA design, embedded systems design, functional verification, and much more.
At Hardent, in addition to our public electronic design courses and Xilinx training schedule, our customers can benefit from personalized training courses and a complete training package tailored to their individual needs.
Personalized training options with Hardent include custom electronic design courses designed and developed for your team, follow-on coaching sessions, electronic design and consulting services, and the opportunity to benefit from the Xilinx Productivity Advantage Program.
We made the decision to work with Hardent as we felt confident that their strategic approach to the development process, combined with their technical expertise and training credentials, would help us to successfully reach our end goal and equip our in-house team with the electronic design knowledge to complete not just this project but other projects in the future.