|On-Demand||Essential Tcl Scripting for the Vivado Design Suite (REL)||Recorded E-Learning||Register||Share||View Course Details|
|On-Demand||Essentials of 7 Series FPGAs (REL)||Recorded E-Learning||Register||Share||View Course Details|
|Oct 07–09, 2015||Designing with Verilog||Montreal, QC||Register||Share||View Course Details|
|Oct 14, 2015||Essential Tcl Scripting for the Vivado Design Suite||Live E-Learning||Register||Share||View Course Details|
|Oct 14, 2015||VESA Display Stream Compression (DSC) Primer||Hsinchu, Taiwan||Register||Share||View Course Details|
|Oct 14–15, 2015||ARM Cortex-M0+ Software Development||Florida||Register||Share||View Course Details|
|Oct 14–16, 2015||Designing with Verilog||New England||Waiting List||Share||View Course Details|
|Oct 15, 2015||Xilinx Partial Reconfiguration Tools and Techniques||Quebec City, QC||Register||Share||View Course Details|
|Oct 16, 2015||VESA Display Stream Compression (DSC) Primer||Shenzhen, China||Register||Share||View Course Details|
|Oct 19, 2015||VESA Display Stream Compression (DSC) Primer||Seoul, South Korea||Register||Share||View Course Details|
|Oct 19–20, 2015||Zynq All Programmable SoC System Architecture||New England||Waiting List||Share||View Course Details|
|Oct 20–22, 2015||Designing with Verilog||Burlington, MA||Register||Share||View Course Details|
|Oct 21, 2015||VESA Display Stream Compression (DSC) Primer||Yokohama, Japan||Register||Share||View Course Details|
|Oct 21–23, 2015||Vivado Design Suite Static Timing Analysis and Design Constraints||New England||Waiting List||Share||View Course Details|
|Oct 21–23, 2015||ARM Cortex-A7 MPCore Software Development||New England||Waiting List||Share||View Course Details|
|Oct 27, 2015||Vivado Design Suite for ISE Project Navigator Users||Canada East||Waiting List||Share||View Course Details|
|Oct 28–29, 2015||Designing with the UltraScale Architecture||Live E-Learning||Register||Share||View Course Details|
|Nov 02–04, 2015||Designing with VHDL||Live E-Learning||Register||Share||View Course Details|
|Nov 02–04, 2015||Vivado Design Suite Static Timing Analysis and Design Constraints||Ottawa, ON||Register||Share||View Course Details|
|Nov 12–14, 2015||Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Design Suite Users||Burlington, MA||Register||Share||View Course Details|
Your first contact at Hardent for more information about our services
Your first contact at Hardent for more information about our services:
Hardent offers technical training courses delivered in person and online. All of our trainers are experienced electronic design and software engineers with extensive hands-on experience in their training fields. As a Xilinx ATP and ARM ATC, we offer a wide range of training programs covering FPGA design, embedded systems design, functional verification, and much more.
Find out more about our electronic design training courses by clicking below.
At Hardent, in addition to our public electronic design courses and Xilinx training schedule, our customers can benefit from personalized training courses and a complete training package tailored to their individual needs.
Personalized training options with Hardent include custom electronic design courses designed and developed for your team, follow-on coaching sessions, electronic design and consulting services, and the opportunity to benefit from the Xilinx Productivity Advantage Program.
Find out more about our custom electronic design training options by clicking below.
We made the decision to work with Hardent as we felt confident that their strategic approach to the development process, combined with their technical expertise and training credentials, would help us to successfully reach our end goal and equip our in-house team with the electronic design knowledge to complete not just this project but other projects in the future.