Advanced Timing Closure Techniques for the Vivado Design Suite

Who Should Attend?

Prerequisites

• FPGA design experience over multiple projects
• Intermediate VHDL or Verilog knowledge
• Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Skills gained

• Explain the impact that manufacturing process variations have on timing analysis and describe how min/max timing analysis information is conveyed in a timing report
• Describe all of the options available with the report_timing and report_timing_summary commands
• Describe the UltraFast design methodology checklist
• Identify key areas to optimize your design to meet your design goals and performance objectives
• Define a properly constrained design
• Build resets into your system for optimum reliability and design speed
• Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
• Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
• Identify timing closure techniques using the Vivado Design Suite
• Describe how the UltraFast design methodology techniques work effectively through case study/lab experience

Course Outline

• UltraFast Design Methodology: Planning - Introduces the methodology guidelines on planning and the UltraFast Design Methodology checklist. {Lecture}
• UltraFast Design Methodology: Design Creation and Analysis - Overview of the methodology guidelines on design creation and analysis.{Lecture}
• HDL Coding Techniques - Covers basic digital coding guidelines used in an FPGA design. {Lecture}
• Resets - Investigates the impact of using asynchronous resets in a design. {Lecture, Lab}
• Baselining and Timing Constraints Validation - Use Xilinx-recommended baselining procedures to progressively meet timing closure and validate timing constraints. {Lecture, Lab}
• Timing Analysis Features and Reports - Use the Vivado Design Suite to analyze pre and post-implementation timing, and use the timing summary report to achieve sign-off criteria for timing closure. {Lecture}
• Synthesis Attributes - Discusses how to use synthesis attributes to alter the design to improve quality of results. {Lecture}
• Analyzing Implementation Results - Analyze the design at different stages to understand and progressively improve results. {Lecture}
• Performing Timing Analysis - Understand how and when to explore timing details using the multitude of reports available within the Vivado Design Suite. {Lecture}
• Understanding Timing Closure Criteria - Investigates proper design methodology for rapid design timing closure. {Lecture}
• CDC Analysis - Covers Vivado Design Suite tools and reports used synchronization circuits to analyze clock domain crossings. {Lecture}
• Analyzing and Resolving Timing Violations - Discusses how to use the Vivado Design Suite to identify the main timing characteristic contributing to each timing violation and apply the correct resolution techniques. {Lecture}
• Timing Methodology Checks - Use Vivado Design Suite Design Rules to identify correct design techniques and timing methodology. {Lecture}
• Synthesis Analysis and Timing Closure - Investigates post-synthesis analysis techniques and options to improve design timing. {Lecture}
• Implementation Analysis and Timing Closure - Investigates post-implementation analysis techniques and options to improve design timing. {Lecture}
• Common Timing Closure Techniques - Discusses techniques and methodology used to address common timing issues. {Lecture}
• Physical Optimization - Use physical optimization techniques for timing closure. {Lecture, Lab}
• Floorplanning - Introduction to Floorplanning and how to use Pblocks while floorplanning. {Lecture, Lab}
• Understanding Congestion - Understand how to identify device congestion with Vivado design flows. {Lecture}
• Incremental Compile Flow - Utilize the incremental compile flow to improve design results. {Lecture, Lab}
• Implementation Strategies and Directives - Discusses how to use implementation strategies and directives to help achieve timing closure on very challenging designs. {Lecture}

Please download the respective PDF of your course: *

• Advanced_Timing_Closure_Techniques_for_the_Vivado_Design_Suite_hdt-tcufdm_2020-1_ilt_H.pdf