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Designing FPGAs Using the Vivado Design Suite 3

FPGA 3

This course demonstrates timing closure techniques, such as baselining, pipelining, synchronization circuits, and optimum HDL coding techniques that help with design timing closure. This course also shows you how to debug your design using advanced capabilities of the Vivado® logic analyzer.
Release date
13 April, 2017
Level
FPGA 3
Training duration
2 day
Price
USD 1600 or 16 Training Credits
Course Part Number
FPGA-VDES3-ILT
Who Should Attend?
FPGA designers with intermediate knowledge of HDL and FPGA architecture and some experience with the Vivado Design Suite
Prerequisites
  • Designing FPGAs Using the Vivado Design Suite 1 course
  • Designing FPGAs Using the Vivado Design Suite 2 course
  • Intermediate HDL knowledge (VHDL or Verilog)
  • Solid digital design background
Software Tools
  • Vivado Design or System Edition 2016.3
Hardware
  • Architecture: UltraScale™ and 7 series FPGAs
  • Demo board: Kintex-7 FPGA KC705 board
Skills gained
After completing this comprehensive training, you will have the necessary skills to:
  • Employ good alternative design practices to improve design reliability
  • Define a properly constrained design
  • Apply baseline constraints to determine if internal timing paths meet design timing objectives
  • Optimize HDL code to maximize the FPGA resources that are inferred and meet performance goals
  • Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
  • Increase performance by utilizing FPGA design techniques
  • Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
Course Outline
  • UltraFast Design Methodology Introduction {Lecture} – Introduces the methodology guidelines covered in this course.
  • Timing Simulation {Lecture, Lab} – Simulate the design post-implementation to verify that a design works properly on hardware.
  • Vivado Design Suite Non-Project Mode {Lecture} – Create a design in the Vivado Design Suite non-project mode.
  • Revision Control Systems in the Vivado Design Suite {Lecture, Lab} – Use version control systems with Vivado design flows.
  • Baselining {Lecture, Lab, Demo} – Use Xilinx-recommended baselining procedures to progressively meet timing closure.
  • Inference {Lecture, Lab} – Infer Xilinx dedicated hardware resources by writing appropriate HDL code.
  • Report Clock Interaction {Lecture, Demo} – Use the clock interaction report to identify interactions between clock domains.
  • Synchronization Circuits {Lecture, Demo} – Use synchronization circuits for clock domain crossings.
  • Report Datasheet {Lecture, Demo} – Use the datasheet report to find the optimal setup and hold margin for an I/O interface.
  • Configuration Modes {Lecture} – Understand various configuration modes and select the suitable mode for a design.
  • Dynamic Power Estimation Using Vivado Report Power {Lecture, Lab} – Use an SAIF (switching activity interface format) file to determine accurate power consumption for a design.
  • Debug Flow in an IP Integrator Block Design {Lecture, Lab} – Insert the debug cores into IP integrator block designs.
  • Remote Debugging Using the Vivado Logic Analyzer {Lecture, Lab} – Use the Vivado logic analyzer to configure an FPGA, set up triggering, and view the sampled data from a remote location.
  • JTAG to AXI Master Core {Lecture, Demo} – Use this debug core to write/read data to/from a peripheral connected to an AXI interface in a system that is running in hardware.
  • Trigger Using the Trigger State Machine in the Vivado Logic Analyzer {Lecture, Lab} – Use trigger state machine code to trigger the ILA and capture data in the Vivado logic analyzer.
  • Manipulating Design Properties Using Tcl {Lecture, Lab} – Query your design and make pin assignments by using various Tcl commands.
Please download the respective PDF of your course: *

Pre-Register

* The course version can be found in the training registration form