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Designing with the UltraScale and UltraScale+ Architectures

This course introduces new and experienced designers to the most sophisticated aspects of the UltraScale and UltraScale+ architectures. Targeted towards designers who have used the Vivado Design Suite, this course focuses on designing for the new and enhanced resources found in our new FPGA families. Topics covered include an introduction to the new CLB resources, the clock management resources (MMCM and PLL), global and regional clocking resources, memory and DSP resources, and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered. In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.
Release date
April 2016
Level
FPGA 3
Training duration
2 days
Price
USD 1600 or 16 Training Credits
Course Part Number
FPGA-US
Who Should Attend?
Anyone who would like to build a design for the UltraScale or UltraScale+ device family
Prerequisites
  • Designing FPGAs Using the Vivado Design Suite 1 course
  • Intermediate VHDL or Verilog knowledge
Software Tools
  • Vivado HL Design or System Edition 2017.1
Hardware
  • Architecture: UltraScale and UltraScale+ FPGAs
  • Demo board: None
Skills gained
After completing this comprehensive training, you will have the necessary skills to:
  • Take advantage of the primary UltraScale architecture resources
  • Describe the new CLB capabilities and the impact that they make on your HDL coding style
  • Define the block RAM, FIFO, and DSP resources available
  • Describe the UltraRAM features
  • Properly design for the I/O and SERDES resources
  • Identify the MMCM, PLL, and clock routing resources included
  • Identify the hard IP resources available for implementing high-performance DDR4 memory interfaces
  • Describe the additional features of the dedicated transceivers
  • Effectively migrate your IP and design to the UltraScale architecture as quickly as possible
Course Outline
  • Introduction to the UltraScale Architecture {Lecture}
  • UltraScale Architecture CLB Resources {Lecture, Lab}
  • HDL Coding Techniques {Lecture, Lab}
  • UltraScale Architecture Clocking Resources {Lectures, Lab}
  • FPGA Design Migration {Lecture, Lab}
  • Clocking Migration {Lab}
  • UltraScale Architecture Block RAM Memory Resources {Lecture}
  • UltraScale Architecture FIFO Memory Resources {Lecture}
  • UltraRAM Memory {Lecture, Lab}
  • UltraScale Architecture DSP Resources {Lecture, Lab}
  • Design Migration Software Recommendations {Lecture}
  • DDR3 MIG Design Migration {Lab}
  • DDR4 Design Creation Using MIG {Lab}
  • UltraScale Architecture I/O Resources Overview {Lecture}
  • UltraScale Architecture I/O Resources – Component Mode {Lecture, Lab}
  • UltraScale Architecture I/O Resources – Native Mode {Lecture, Lab}
  • Design Migration Methodology {Lecture}
  • 10G PCS/PMA and MAC Design Migration {Lab}
  • UltraScale Architecture Transceivers {Lecture}
  • UltraScale FPGAs Transceivers Wizard {Lecture, Lab, Demo}
  • Introduction to the UltraScale+ Families {Lecture}
Special Comments
Please download the respective PDF of your course: *

* The course version can be found in the training registration form