Introduction to the Zynq SoC Architecture

• Describing the architecture of the ARM® Cortex™-A9 processor-based processing system (PS) and the integration of programmable logic (PL)
• Detailing the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers
• Effectively accessing and using the PS DDR controller from PL user logic
• Interfacing PL-to-PS efficiently
• Employing best practice design techniques for implementing functions in the PS or PL

Who Should Attend?

Prerequisites

• FPGA design experience
• Completion of the Designing FPGAs Using the Vivado Design Suite 1 course or equivalent knowledge of the Vivado Design Suite implementation tools
• Basic understanding of C programming
• Basic understanding of microprocessors
• Some HDL modeling experience

Skills gained

• Describe the architecture and components that comprise the Zynq SoC processing system (PS)
• Evaluate a processing system (PS) and programmable logic (PL) AXI interface
• Identify the boot options for the Zynq SoC

Course Outline

• Overview - Provides a general overview of the Zynq SoC. {Demo}
• Application Processor Unit (APU) - Explores the individual components that comprise the APU. {Lab}
• Input/Output Peripherals - Introduces the components that comprise the IOP block of the Zynq device PS. {Demo}
• PS-PL Interface - Describes in detail the PS interconnect and how it affects PL architecture decisions. {Demo, Lab}
• Memory Resources - Explains the operation of the on-chip (OCM) memory and various memory controllers located in the PS. {Demo}
• Booting - Explains the boot process of the PC and configuration of the PL. {Lab}

Special Comments

Please download the respective PDF of your course: *

• Introduction_to_Zynq_SoC_Architecture_embd-introzarch_2020-1_ilt_H.pdf