Learn how to implement a system on a chip using the Zynq SoC and programmable logic.
This course, available in-person or online, provides hardware and firmware engineers with the knowledge to effectively
utilize a Zynq System on a Chip (SoC). It covers the architecture
of the ARM Cortex-A9 processor-based processing system (PS) and the integration of
programmable logic (PL).
The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.
The course details the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers. Emphasis is placed on effective access and usage of the PS DDR controller from PL user logic, efficient PL-to-PS interfacing, and design techniques, tradeoffs, and advantages of implementing functions in the PS or the PL.
Release date
August 2016Level
Embedded Hardware and Firmware 3Training duration
1 dayPrice
USD 800 or 8 Training CreditsCourse Part Number
EMBD-INTROZARCHWho Should Attend?
Hardware and firmware engineers who are interested in implementing a system on a chip using the Zynq SoC and programmable logic.Prerequisites
- FPGA design experience
- Completion of the Designing FPGAs Using the Vivado Design Suite 1 course or equivalent knowledge of the Vivado Design Suite implementation tools
- Basic understanding of C programming
- Basic understanding of microprocessors
- Some HDL modeling experience
Software Tools
- Vivado Design or System Edition 2018.1
Hardware
- Architecture: Zynq-7000 SoC
- Demo board: Zynq-7000 SoC ZC702 or ZedBoard*
Skills gained
After completing this comprehensive training, you will have the necessary skills to:- Describe the architecture and components that comprise the Zynq SoC processing system (PS)
- Evaluate a processing system (PS) and programmable logic (PL) AXI interface
- Identify the configuration options for the Zynq SoC
Course Outline
- Overview {Lecture, Demo}
- Application Processor Unit (APU) {Lecture, Lab}
- Processor Input/Output Peripherals {Lecture, Demo}
- PS-PL Interface {Lecture, Demo, Lab}
- Booting {Lecture, Lab}
- Memory Resources {Lecture, Demo}
Topic Descriptions
- Overview – Provides a general overview of the Zynq SoC.
- Application Processor Unit (APU) – Explores the individual components that comprise the APU.
- Processor Input/Output Peripherals – Introduces the components that comprise the IOP block of the Zynq device PS.
- PS-PL Interface – Describes in detail the PS interconnect and how it affects PL architecture decisions.
- Booting – Explains the boot process of the PC and configuration of the PL.
- Memory Resources {Lecture, Demo} – Explains the operation of the on-chip (OCM) memory and various memory controllers located in the PS.
Special Comments
*The listed course price is for the in-person training. The cost of the online training is $1200 or 12 Training Credits and includes a ZedBoard that is yours to keep after the training is completed. If you already own a ZedBoard, the overall cost of the online training remains at $800 or 8 Training Credits.Please download the respective PDF of your course: *
* The course version can be found in the training registration form