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Introduction to the Zynq SoC Architecture

Learn how to implement a system on a chip using the Zynq SoC and programmable logic.

This course provides hardware and firmware engineers with the knowledge on how to best architect a Zynq® System on a Chip (SoC) device project.

This course covers:
  • Describing the architecture of the ARM® Cortex™-A9 processor-based processing system (PS) and the integration of programmable logic (PL)
  • Detailing the individual components that comprise the PS: I/O peripherals, timers, caching, DMA, interrupt, and memory controllers
  • Effectively accessing and using the PS DDR controller from PL user logic
  • Interfacing PL-to-PS efficiently
  • Employing best practice design techniques for implementing functions in the PS or PL

Release date

August 2016

Level

Embedded Hardware and Firmware 3

Training duration

1 day

Price

USD 800 or 8 Training Credits

Course Part Number

EMBD-INTROZARCH

Who Should Attend?

Hardware and firmware engineers who are interested in implementing a system on a chip using the Zynq SoC and programmable logic.

Prerequisites

  • FPGA design experience
  • Completion of the Designing FPGAs Using the Vivado Design Suite 1 course or equivalent knowledge of the Vivado Design Suite implementation tools
  • Basic understanding of C programming
  • Basic understanding of microprocessors
  • Some HDL modeling experience

Software Tools

  • Vivado® Design Suite 2020.1
  • Vitis™ unified software platform 2020.1

Hardware

  • Architecture: Zynq-7000 SoC
  • Demo board: Zynq-7000 SoC ZC702 or ZedBoard*

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Describe the architecture and components that comprise the Zynq SoC processing system (PS)
  • Evaluate a processing system (PS) and programmable logic (PL) AXI interface
  • Identify the boot options for the Zynq SoC

Course Outline

  • Overview - Provides a general overview of the Zynq SoC. {Demo}
  • Application Processor Unit (APU) - Explores the individual components that comprise the APU. {Lab}
  • Input/Output Peripherals - Introduces the components that comprise the IOP block of the Zynq device PS. {Demo}
  • PS-PL Interface - Describes in detail the PS interconnect and how it affects PL architecture decisions. {Demo, Lab}
  • Memory Resources - Explains the operation of the on-chip (OCM) memory and various memory controllers located in the PS. {Demo}
  • Booting - Explains the boot process of the PC and configuration of the PL. {Lab}

Special Comments

*The listed course price is for the in-person training. The cost of the online training is $1200 or 12 Training Credits and includes a ZedBoard that is yours to keep after the training is completed. If you already own a ZedBoard, the overall cost of the online training remains at $800 or 8 Training Credits.

Please download the respective PDF of your course: *

  • Introduction_to_Zynq_SoC_Architecture_embd-introzarch_2020-1_ilt_H.pdf

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* The course version can be found in the training registration form
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Course Schedule

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Training Funding

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Upcoming Sessions
Mar 03–04
Designing with Versal AI Engine 2
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Mar 08–11
Designing with the Versal ACAP: Architecture and Methodology
Register
Mar 08–10
Advanced Timing Closure Techniques for the Vivado Design Suite
Register
Mar 15–18
Introduction to UVM
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Complete Course Schedule
Contact Hardent
Your Trainer, Reg
Have a question about the course?
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