Learn how to use basic Tcl syntax and language structures to build scripts suitable for use with Xilinx FPGA design tools. Learn about the effective use of variables, data types, and Tcl constructs to build effective conditional statements and loop controls. You will also have the opportunity to use Tcl language constructs with several labs designed to provide you scripting experience within the Vivado™ Design Suite.
Release dateJuly 2012
Training duration5-8 hours (available online for 30 days)
PriceUSD 500 or 5 Training Credits
Course Part NumberLANG13000
Who Should Attend?FPGA designers and logic designers
- FPGA design experience
- Vivado System Edition 2012.2
- Architecture: N/A
- Demo board: None
Skills gainedAfter completing this comprehensive training, you will have the necessary skills to:
- Describe the basic syntax and language structure of the Tcl language
- Execute Tcl commands from a script using the Vivado IDE
- Use variables and describe data types
- Use Tcl language constructs to build conditional statements and loop controls for some common FPGA applications
- Use lists and arrays in efficient data structures
- Use procedures, packages, and namespaces to develop modules
- Using Tcl in the Vivado IDE
- Basic Syntax and Structure
- Lab 1: Xilinx Tcl Scripting
- Data Types, Variables, and Expressions
- Conditional Expressions and Loops
- Lab 2: Manipulating Pin Attributes with Tcl
- Data Structures in Tcl
- Procedures and Packages
- Lab 3: Design Analysis with the Vivado IDE
- Xilinx Tcl Regular Expressions
- Lab 4: Using Regular Expressions
- Appendix: Debugging and Error Management
- Appendix: Using Tcl in the Xilinx Environment
- Lab 1: Basic Tcl Scripting - Learn how to use Tcl scripts in a typical FPGA design flow using the Vivado IDE.
- Lab 2: Manipulating Pin Attributes with Tcl - Learn to query your design netlist and verify the use of various Tcl commands with the Vivado IDE. You will also learn to make pin assignments and verify resource usage with appropriate Vivado IDE reports.
- Lab 3: Design Analysis with the Vivado IDE - This lab introduces some of the most important reporting and design analysis features provided by the Vivado Design Suite. In this lab, you will use Tcl commands to query the design netlist and locate clock sources. You will also use the check_timing and report_timing commands to verify design performance.
- Lab 4: Using Regular Expressions - Query timing reports to find critical timing information and build a custom timing report while using file I/O commands and regular expressions to extract essential information with a script.
Please download the respective PDF of your course: *
* The course version can be found in the training registration form