This 4-day workshop introduces the student to the SystemC C++ class library
and the TLM 2.0 modeling standard. It is intended for engineers who are new to SystemC
or those who may be self-taught, with an interest in learning SystemC for modeling purposes.
The student will learn how to write, compile, execute, and debug system and hardware descriptions
with SystemC, and will receive thorough and in-depth coverage of the concepts of the Accellera/IEEE
TLM 2.0 modeling standard.
This course is mixed lecture and exercises, with an exercise for nearly every topic.
Release date
July 14, 2016Level
1Training duration
4 daysPrice
USD 3200 or 32 Training CreditsCourse Part Number
HDT-SYSCINTROTLM-100Who Should Attend?
Engineers who want to model complex SOC systems using C++ with the latest
IEEE 1666 SystemC core library and TLM 2.0 library.
Prerequisites
- Strong knowledge of C++
Software Tools
- Questa Simulator 10.4c
Skills gained
After completing this comprehensive training, you will have the necessary skills to:- Create fast, transaction-level simulation models of complex SOC systems
- Create system models for developing and tuning firmware and software without the need to wait for RTL or emulation models
- Analyze SOC performance parameters such as bus utilization and cache requirements
- Develop complex prediction models for verification
Course Outline
- Introduction to SystemC
- • Core Library Basics
- o Modules
- o Communication (channels, ports, and exports)
- o Module Constructor (and exercise)
- o Simulation
- o Scheduler
- o Events and Event Queues
- • Modeling Behavior
- o Method Processes (and exercise)
- o Thread Processes (and exercise)
- o Module Instantiation (in module) (and exercise)
- o Simulation Initialization
- • Core Library Elements
- o SystemC Data Types
- o Primitive Channels
- • User-defined Channels (and exercise)
- o Custom Constructors
- • Exports
- • Dynamic Processes (and exercise)
- Introduction to the IEEE TLM 2.0 Standard
- • TLM 2.0 Overview
- o Interface Functions
- o Sockets
- o Generic Payload
- o Protocol
- • Interfaces
- o Transport
- o DMI
- o Debug
- • Sockets
- o Initiator and Target
- o Socket Binding
- o Hierarchy, Multi-connect
- o Topology Examples
- • Generic Payload Overview
- o Attributes
- • LT Coding style (and exercise)
- o Transport Interface
- o Temporal Decoupling
- o Temporal Decoupling
- • AT Coding Style (and exercise)
- o Protocol Phases
- o Forward, Backward, and Return Paths
- o Base Protocol (2-phase)
- o Payload Event Queue (PEQ)
- • DMI Interface
- o DMI Hint
- o DMI Data Structure
- o Invalidating DMI
- • Debug Interface (and exercise)
- o Debug Transport Interface
- • Convenience Sockets (and exercise)
- o Simple Sockets
- o Tagged Sockets
- o Multi-passthrough Sockets
- • Generic Payload In-depth
- o Byte Enable
- o Streaming
- o Endianness
- o Memory Management
- • Generic Payload Extensions (and exercise)
- • Base Protocol In-depth
- o 4-state and Variants
Please download the respective PDF of your course: *
* The course version can be found in the training registration form