This is a one-day version of the Designing with the UltraScale Architecture course and introduces new and experienced designers to the most sophisticated aspects of the UltraScale and UltraScale+ architectures. Targeted towards designers who have used the Vivado Design Suite, this course focuses on designing for the new and enhanced resources found in our newest FPGA family. Topics covered include an introduction to the clock management resources (MMCM and PLL), global and regional clocking resources, memory resources, and source-synchronous resources. A description of the improvements to the dedicated transceivers and Transceiver Wizard is also included. Use of the Memory Interface Generator (MIG) and the new DDR4 memory interface capabilities is also covered. In addition, you will learn how to best migrate your design and IP to the UltraScale architecture and the best way to use the Vivado Design Suite during design migration. A combination of modules and labs allow for practical hands-on experience of the principles taught.
Release dateApril 2016
Training duration1 day
PriceUSD 600 or 6 Training Credits
Course Part NumberFPGA-US1D
Who Should Attend?Anyone who would like to build a design for the UltraScale or UltraScale+ device family
- Completion of the Essentials of FPGA Design course and Vivado Design Suite STA and Xilinx Design Constraints course
- OR completion of the Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Software Users course
- Vivado Design or System Edition 2016.1
- Architecture: UltraScale and UltraScale+ FPGAs
- Demo board: None
Skills gainedAfter completing this comprehensive training, you will have the necessary skills to:
- Take advantage of the primary UltraScale architecture resources
- Define the block RAM and FIFO resources available for UltraScale FPGAs
- Describe the UltraRAM features
- Properly design for the I/O and SERDES resources
- Identify the MMCM, PLL, and clock routing resources included with the UltraScale architecture
- Identify the hard IP resources available for implementing high-performance DDR4 physical layer interfaces
- Describe the additional features of the dedicated transceivers
- Effectively migrate your IP and design to the UltraScale architecture as quickly as possible
- Clocking Resources
- Lab 1: Clocking Resources
- Memory Resources
- Lab 2: DDR4 MIG Design Creation
- I/O Resources
- Lab 3: SelectIO Design (Component Mode)
- FPGA Design Migration
- Lab 4: QSGMII Design Migration
- Transceiver Overview
- Lab 5: Transceiver Core Resources
- Lab 1: Clocking Resources - Use the Clocking Wizard to configure a clocking subsystem to provide various clock outputs and distribute them on the dedicated global clock networks.
- Lab 2: DDR4 MIG Design Creation - Create a DDR4 memory controller with the Memory Interface Generator (MIG) utility.
- Lab 3: SelectIO Design (Component Mode) - Implement a high-performance, source-synchronous interface using the UltraScale architecture SelectIO in component mode.
- Lab 4: QSGMII Design Migration - Migrate an existing 7 series QSGMII example design to a Kintex UltraScale architecture-based device. This lab will show you how to update your port connections and use the optimum logic resources available.
- Lab 5: Transceiver Core Resources - Use the Transceiver Wizard to build a design that uses a single serial transceiver and observe the file structures created.
Please download the respective PDF of your course: *
* The course version can be found in the training registration form