Verilog Fundamentals for SystemVerilog

This 1-day course introduces engineers with “e” (Specman) or VHDL experience to the fundamentals of Verilog in preparation to learning SystemVerilog and is typically taught in conjunction with the Introduction to SystemVerilog course. The course covers the fundamental features of Verilog in a condensed manner. It is not intended to teach Verilog design skills.

VHDL engineers who wish to learn SystemVerilog and “e” engineers who wish to learn SystemVerilog.

After completing this comprehensive training, you will have the necessary skills to:

• Understand the fundamental types and code structures of the Verilog hardware description language
• Proceed to the SystemVerilog for Verification Training course