Get ready to learn SystemVerilog with this 1-day Verilog fundamentals training course.
This 1-day course introduces engineers with “e” (Specman) or VHDL experience to the fundamentals of Verilog in preparation to learning SystemVerilog and is typically taught in conjunction with the Introduction to SystemVerilog course. The course covers the fundamental features of Verilog in a condensed manner. It is not intended to teach Verilog design skills.
Release dateJune 27, 2016
Training duration1 day
PriceUSD 800 or 8 Training Credits
Course Part NumberWHDL-VERFUNSYSVER-100
Who Should Attend?VHDL engineers who wish to learn SystemVerilog and “e” engineers who wish to learn SystemVerilog.
- VHDL or "e" experience
- Questa Simulator 10.4c
Skills gainedAfter completing this comprehensive training, you will have the necessary skills to:
- Understand the fundamental types and code structures of the Verilog hardware description language
- Proceed to the SystemVerilog for Verification Training course
- Data types
- Procedural assignments
- Connecting and driving ports
- Lab - Modules
- Programming statements
- Lab - Programming statements
Please download the respective PDF of your course: *
* The course version can be found in the training registration form