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Verilog Fundamentals for SystemVerilog

Get ready to learn SystemVerilog with this 1-day Verilog fundamentals training course.

This 1-day course introduces engineers with “e” (Specman) or VHDL experience to the fundamentals of Verilog in preparation to learning SystemVerilog and is typically taught in conjunction with the Introduction to SystemVerilog course. The course covers the fundamental features of Verilog in a condensed manner. It is not intended to teach Verilog design skills.

Release date

June 27, 2016

Level

1

Training duration

1 day

Price

USD 800 or 8 Training Credits

Course Part Number

WHDL-VERFUNSYSVER-100

Who Should Attend?

VHDL engineers who wish to learn SystemVerilog and “e” engineers who wish to learn SystemVerilog.

Prerequisites

  • VHDL or "e" experience

Software Tools

  • Questa Simulator 10.4c

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Understand the fundamental types and code structures of the Verilog hardware description language
  • Proceed to the SystemVerilog for Verification Training course

Course Outline

  • Data types
  • Modules
    • Ports
    • Instances
    • Processes
    • Scheduler
    • Procedural assignments
    • Connecting and driving ports
    • Lab - Modules
  • Operators
  • Programming statements
  • Lab - Programming statements

Please download the respective PDF of your course: *

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