Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Who Should Attend?

Prerequisites

• FPGA design experience over multiple projects
• Intermediate VHDL or Verilog knowledge
• FPGA Design with Vivado Design Suite: The Essentials
• Improve Your Vivado Design Suite Productivity
• Essential Tcl Scripting for the Vivado Design Suite (Recommended)

Skills gained

• Access primary objects from the design database and filter lists of objects using properties
• Describe setup and hold checks and describe the components of a timing report
• Create appropriate input and output delay constraints and describe timing reports that involve input and output paths
• Explain the impact that manufacturing process variations have on timing analysis and describe how min/max timing analysis information is conveyed in a timing report
• Describe all the options available with the report_timing and report_timing_summary commands
• Describe the timing constraints required to constrain system-synchronous and source-synchronous interfaces
• Analyze a timing report to identify how to center the clock in the data eye
• Create scripts for the project-based and non-project batch design flows
• Describe the UltraFast design methodology checklist
• Identify key areas to optimize your design to meet your design goals and performance objectives
• Define a properly constrained design
• Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
• Build resets into your system for optimum reliability and design speed
• Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
• Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
• Identify timing closure techniques using the Vivado Design Suite
• Describe how the UltraFast design methodology techniques work effectively through case study/lab experience

Course Outline

• Vivado Design Suite Project Mode - Create a project, add files to the project, explore the Vivado IDE, and simulate the design. {Lecture, Lab}
• Using Tcl Commands in the Vivado Design Suite Project Flow - Explains what Tcl commands are executed in a Vivado Design Suite project flow. {Lecture}
• Design Analysis Using Tcl Commands - Analyze a design using Tcl commands. {Lecture, Lab}
• Introduction to Clock Constraints - Apply clock constraints and perform timing analysis. {Lecture, Lab}
• Generated Clocks - Use the report clock networks report to determine if there are any generated clocks in a design. {Lecture}
• Setup and Hold Timing Analysis - Understand setup and hold timing analysis. {Lecture}
• Timing Constraints Editor - Introduces the timing constraints editor tool to create timing constraints. {Lecture}
• Timing Constraints Wizard - Use the Timing Constraints Wizard to apply missing timing constraints in a design. {Lecture, Lab}
• Introduction to Vivado Reports - Generate and use Vivado timing reports to analyze failed timing paths. {Lecture}
• Report Clock Interaction - Use the clock interaction report to identify interactions between clock domains. { {Lecture}
• Report Clocks Networks - Use report clock networks to view the primary and generated clocks in a design. {Lecture}
• I/O Constraints and Virtual Clocks - Apply I/O constraints and perform timing analysis. {Lecture, Lab}
• Timing Summary Report - Use the post-implementation timing summary report to sign-off criteria for timing closure. {Lecture}
• Introduction to Timing Exceptions - Introduces timing exception constraints and applying them to fine tune design timing. {Lecture, Lab}
• Clock Group Constraints - Apply clock group constraints for asynchronous clock domains.{Lecture}
• Timing Constraints Priority - Identify the priority of timing constraints. {Lecture, Demo}
• I/O Timing Scenarios - Overview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture, and edge/center aligned data. {Lecture}
• System-Synchronous I/O Timing - Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface. {Lecture}
• Source-Synchronous I/O Timing - Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface. {Lecture, Lab}
• Report Datasheet - Use the datasheet report to find the optimal setup and hold margin for an I/O interface. {Lecture}
• Case Analysis - Understand how to analyze timing when using multiplexed clocks in a design. {Lecture}
• UltraFast Design Methodology: Introduction - Introduces the UltraFast Design Methodology and the UltraFast Design Methodology checklist.{Lecture}
• UltraFast Design Methodology: Planning - Introduces the methodology guidelines on planning and the UltraFast Design Methodology checklist. {Lecture}
• UltraFast Design Methodology Design Creation and Analysis - Overview of the methodology guidelines on design creation and analysis.{Lecture}
• HDL Coding Techniques - Covers basic digital coding guidelines used in an FPGA design. {Lecture}
• Resets - Investigates the impact of using asynchronous resets in a design. {Lecture, Lab}
• Register Duplication - Use register duplication to reduce high fanout nets in a design. {Lecture}
• Baselining - Use Xilinx-recommended baselining procedures to progressively meet timing closure. {Lecture, Lab}
• Synchronization Circuits - Use synchronization circuits for clock domain crossings. {Lecture}
• Revision Control Systems in the Vivado Design Suite - Use version control systems with Vivado design flows. {Lecture}
• Physical Optimization - Use physical optimization techniques for timing closure. {Lecture, Lab}

Please download the respective PDF of your course: *

• Vivado_Design_Suite_Advanced_XDC_and_Static_Timing_Analysis_with_Design_Methodology_fpga-xdcvdm-ilt_2020-1_ilt_H.pdf