Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Who Should Attend?

Prerequisites

• FPGA design experience
• Completion of the Essentials of FPGA Design, Designing for Performance, and Advanced FPGA Implementation courses or equivalent knowledge of Xilinx ISE software implementation tools, techniques, architecture, and FPGA design techniques. Completion of the Vivado Design Suite for ISE Project Navigator Users course is strongly recommended.
• Intermediate VHDL or Verilog knowledge

Recommended Prerequisites

• Essential Tcl Scripting for the Vivado Design Suite course
• Vivado Design Suite for ISE Software Project Navigator Users course

Skills gained

• Access primary objects from the design database and filter lists of objects using properties
• Describe setup and hold checks and describe the components of a timing report
• Create appropriate input and output delay constraints and describe timing reports that involve input and output paths
• Explain the impact that manufacturing process variations have on timing analysis and describe how min/max timing analysis information is conveyed in a timing report
• Describe all the options available with the report_timing and report_timing_summary commands
• Describe the timing constraints required to constrain system-synchronous and source-synchronous interfaces
• Analyze a timing report to identify how to center the clock in the data eye
• Create scripts for the project-based and non-project batch design flows
• Describe the UltraFast design methodology checklist
• Identify key areas to optimize your design to meet your design goals and performance objectives
• Define a properly constrained design
• Optimize HDL code to maximize the FPGA resources that are inferred and meet your performance goals
• Build resets into your system for optimum reliability and design speed
• Build a more reliable design that is less vulnerable to metastability problems and requires less design debugging later in the development cycle
• Use Vivado Design Suite reports and utilities to full advantage, especially the Clock Interaction report
• Identify timing closure techniques using the Vivado Design Suite
• Describe how the UltraFast design methodology techniques work effectively through case study/lab experience

Course Outline

• Vivado Design Suite Project Mode {Lecture, Lab}
• Using Tcl Commands in the Vivado Design Suite Project Flow {Lecture}
• Design Analysis Using Tcl Commands {Lecture, Lab, Demo}
• Introduction to Clock Constraints {Lecture, Lab}
• Generated Clocks {Lecture}
• Setup and Hold Timing Analysis {Lecture}
• Timing Constraints Editor {Lecture}
• Timing Constraints Wizard {Lecture, Lab}
• Introduction to Vivado Reports {Lecture}
• Report Clock Interaction {Lecture}
• Report Clocks Networks {Lecture}
• I/O Constraints and Virtual Clocks {Lecture, Lab}
• Timing Summary Report {Lecture}
• Introduction to Timing Exceptions {Lecture, Lab}
• Clock Group Constraints {Lecture}
• Timing Constraints Priority {Lecture, Demo}
• I/O Timing Scenarios {Lecture}
• System-Synchronous I/O Timing {Lecture}
• Source-Synchronous I/O Timing {Lecture, Lab}
• Report Datasheet {Lecture}
• Case Analysis {Lecture}
• UltraFast Design Methodology: Introduction {Lecture}
• UltraFast Design Methodology: Planning {Lecture}
• UltraFast Design Methodology Design Creation and Analysis {Lecture}
• HDL Coding Techniques {Lecture}
• Resets {Lecture, Lab}
• Register Duplication {Lecture}
• Baselining {Lecture, Lab}
• Synchronization Circuits {Lecture}
• Revision Control Systems in the Vivado Design Suite {Lecture}
• Physical Optimization {Lecture, Lab}

Topic Descriptions

• Vivado Design Suite Project Mode – Create a project, add files to the project, explore the Vivado IDE, and simulate the design.
• Using Tcl Commands in the Vivado Design Suite Project Flow – Explains what Tcl commands are executed in a Vivado Design Suite project flow.
• Design Analysis Using Tcl Commands – Analyze a design using Tcl commands.
• Introduction to Clock Constraints – Apply clock constraints and perform timing analysis.
• Generated Clocks – Use the report clock networks report to determine if there are any generated clocks in a design.
• Setup and Hold Timing Analysis – Understand setup and hold timing analysis.
• Timing Constraints Editor – Introduces the timing constraints editor tool to create timing constraints.
• Timing Constraints Wizard – Use the Timing Constraints Wizard to apply missing timing constraints in a design.
• Introduction to Vivado Reports – Generate and use Vivado timing reports to analyze failed timing paths.
• Report Clock Interaction – Use the clock interaction report to identify interactions between clock domains.
• Report Clocks Networks – Use report clock networks to view the primary and generated clocks in a design.
• I/O Constraints and Virtual Clocks – Apply I/O constraints and perform timing analysis.
• Timing Summary Report – Use the post-implementation timing summary report to sign-off criteria for timing closure.
• Introduction to Timing Exceptions – Introduces timing exception constraints and applying them to fine tune design timing.
• Clock Group Constraints – Apply clock group constraints for asynchronous clock domains.
• Timing Constraints Priority – Identify the priority of timing constraints.
• I/O Timing Scenarios – Overview of various I/O timing scenarios, such as source- and system-synchronous, direct/MMCM capture, and edge/center aligned data.
• System-Synchronous I/O Timing – Apply I/O delay constraints and perform static timing analysis for a system-synchronous input interface.
• Source-Synchronous I/O Timing – Apply I/O delay constraints and perform static timing analysis for a source-synchronous, double data rate (DDR) interface.
• Report Datasheet – Use the datasheet report to find the optimal setup and hold margin for an I/O interface.
• Case Analysis – Understand how to analyze timing when using multiplexed clocks in a design.
• UltraFast Design Methodology: Introduction – Introduces the UltraFast Design Methodology and the UltraFast Design Methodology checklist.
• UltraFast Design Methodology: Planning – Introduces the methodology guidelines on planning and the UltraFast Design Methodology checklist.
• UltraFast Design Methodology Design Creation and Analysis – Overview of the methodology guidelines on design creation and analysis.
• HDL Coding Techniques – Covers basic digital coding guidelines used in an FPGA design.
• Resets – Investigates the impact of using asynchronous resets in a design.
• Register Duplication – Use register duplication to reduce high fanout nets in a design.
• Baselining – Use Xilinx-recommended baselining procedures to progressively meet timing closure.
• Synchronization Circuits – Use synchronization circuits for clock domain crossings.
• Revision Control Systems in the Vivado Design Suite – Use version control systems with Vivado design flows.
• Physical Optimization – Use physical optimization techniques for timing closure.

Please download the respective PDF of your course: *

• Vivado_Design_Suite_Advanced_XDC_and_Static_Timing_Analysis_with_Design_Methodology_fpga-xdcvdm-ilt_2018-3_ilt_H.pdf