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Xilinx & Verification Training Courses
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Webinar: Algorithm Acceleration Using Xilinx Platforms (REL)

This pre-recorded webinar shows how you can use the Xilinx development portfolio for algorithm acceleration.

This webinar will provide an introduction to using Xilinx platforms to accelerate software algorithms. We will explore how both software and hardware engineers can use the complete Xilinx development portfolio, including server solutions, hardware devices, and software platforms, to leverage their various skill sets and minimize development time on projects requiring algorithm acceleration.

Attendees will learn about hardware and software solutions that they can use to develop and deploy highly accelerated algorithms for a wide variety of applications, including data analytics, machine learning and AI, video and image processing, finance, and genomics.

Release date

February 18, 2021

Level

Training duration

Price

Free

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Learn about Xilinx accelerator cards for servers
  • Learn about using Versal ACAPs for algorithm acceleration
  • Discover new software tools and flows to improve productivity
  • Learn about integrated hardware/software simulation flows and design methodology

* The course version can be found in the training registration form

Related Courses

Accelerating Applications with the Vitis Unified Software Environment

View course

Designing with the Versal ACAP: Embedded Processor Architecture and Methodology

View course

Migrating to the Vitis Embedded Software Development IDE Workshop

View course
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Course Schedule

  • On-Demand
    On-Demand
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Wondering Which Course to Take?

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Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

See our list of resources
Upcoming Sessions
Mar 03–04
Designing with Versal AI Engine 2
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Mar 08–11
Designing with the Versal ACAP: Architecture and Methodology
Register
Mar 08–10
Advanced Timing Closure Techniques for the Vivado Design Suite
Register
Mar 15–18
Introduction to UVM
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Complete Course Schedule
Latest News
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PLC2 named as the official IP representative for Hardent’s video compression IP cores in Germany, Austria, and Switzerland.
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Upcoming Sessions
Mar 03–04
Designing with Versal AI Engine 2
Register
Mar 08–11
Designing with the Versal ACAP: Architecture and Methodology
Register
Mar 08–10
Advanced Timing Closure Techniques for the Vivado Design Suite
Register
Mar 15–18
Introduction to UVM
Register
Complete Course Schedule
Contact Hardent
Your Trainer, Reg
Have a question about the course?
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