This webinar is free to watch. A link to the recording will be provided shortly after registration.
As designs become more complex, it becomes more difficult, if not impossible, to write enough
directed tests to fully verify functionality. Most methodologies add randomization to help generate
a broader set of input stimuli, but this makes it even more vital to somehow define and measure our
progress toward our verification goals. This is where functional coverage comes in.
This webinar will introduce the basics of functional coverage in SystemVerilog. We will discuss how to
specify your coverage goals, how to use coverage metrics during simulation, and even how to stop simulation
when your goals are reached.The webinar is presented by Xilinx Authorized Training Provider Hardent.
Release date
May 25, 2017Level
Training duration
Price
Please inquire for pricingSkills gained
After completing this comprehensive training, you will have the necessary skills to:- Learn the basics of functional coverage in SystemVerilog
- Recognize the importance of functional coverage
- Discover how to define covergroups, coverpoints, and bins
- Learn how to interrogate the functional coverage database “live” during simulation
* The course version can be found in the training registration form