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Xilinx & Verification Training Courses
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Webinar: Getting Started With Xilinx Zynq UltraScale+ MPSoCs (REL)

This pre-recorded webinar will give you an introduction to the main architecture components of Xilinx Zynq UltraScale+ MPSoCs.

Xilinx Zynq UltraScale+ MPSoC devices provide 64-bit processor scalability while combining real-time control with soft and hard engines for graphics, video, waveform, and packet processing. Built on a common processor and programmable logic equipped platform, three distinct variants include dual application processor (CG) devices, quad application processor and GPU (EG) devices, and video codec (EV) devices, creating unlimited possibilities for applications such as 5G Wireless, next-generation Advanced Driver Assistance Systems, and Industrial Internet-of-Things.

The webinar is presented by Xilinx Authorized Training Provider Hardent.

Release date

November 13, 2018

Level

Training duration

Price

Free

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Learn about the different processing units that are included in the Processing System
  • Understand the use-case for each of the processing units
  • Become familiar with the additional building blocks that round out the highly integrated MPSoC devices
  • Come to appreciate the wide range of supported software architectures
  • Understand the concepts and capabilities of the security features built into the MPSoC devices
  • Leave with a greater understanding of both the hardware and software development environments offered by Xilinx

* The course version can be found in the training registration form

Related Courses

Embedded System Design for the Zynq UltraScale+ MPSoC

View course

Zynq UltraScale+ MPSoC for the System Architect

View course
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Mary-Ann Conly
Training Coordinator

Course Schedule

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Designing with Versal AI Engine 2
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Introduction to UVM
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Designing with the Versal ACAP: Embedded Processor Architecture and Methodology
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Advanced Hardware Debugging Techniques Using Vivado Design Suite
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Upcoming Sessions
Jan 27–28
Designing with Versal AI Engine 2
Register
Feb 01–04
Introduction to UVM
Register
Feb 02–03
Designing with the Versal ACAP: Embedded Processor Architecture and Methodology
Register
Feb 03–04
Advanced Hardware Debugging Techniques Using Vivado Design Suite
Register
Complete Course Schedule
Contact Hardent
Mary-Ann Conly
Training Coordinator
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I’ve worked with Hardent for many years and have recommended them a few times in the past. Hardent has always been extremely successful with their clients. They have many flexible ways of working with a client and will negotiate a mutually beneficial solution.

In our case, they just log into our servers and we are in constant contact via IM, email, phone, etc., but they have all their own design tools as well, so they can work either way. Being in the same time zone makes working with them easy. I am sure you will be happy with the outcome of their work. They’ll hit the ground running much faster than a single contractor would.

Marshall Johnson
Sr. Director Global ASIC/FPGA/IP Development
ADVA Optical Networking
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