This webinar is free to watch. A link to the recording will be provided shortly after registration.
Heterogeneous (multi-processor) devices require a more complex software architecture capable of orchestrating multiple, dissimilar processors. While heterogeneous SoCs are by no means a “new” concept, in the past developers generally only had "raw" access to one processor architecture, on which firmware could be run, with other architectures abstracted away through libraries or tools. Now, however, we're seeing chips that give the developer direct access to multiple architectures. The Xilinx Zynq UltraScale MPSoC is one such example with four ARM Cortex-A53 cores and two Cortex-R5 cores. Additionally, MicroBlaze “soft” processor cores can be added to the FPGA of all Zynq SoC and MPSoC devices. Using the Xilinx Zynq-7000 SoC and Zynq UltraScale MPSoC as examples, this webinar will look at what the OpenAMP framework is and outline how designers can leverage the framework to run different software platforms concurrently, such as Linux and an RTOS, on different processors within the same SoC whether homogeneous (multi-core), or heterogeneous (multi-processor), or a combination of both. Please note that there is an issue with the audio in the recording that resolves after the first 3 minutes and 50 seconds. The webinar is presented by Xilinx Authorized Training Provider Hardent.
Release dateJuly 7, 2017
PricePlease inquire for pricing
Skills gainedAfter completing this comprehensive training, you will have the necessary skills to:
- Learn about Linux Asymmetric Multiprocessing (AMP) on multi-core and heterogeneous devices
- Discover what the OpenAMP framework is and how it can be utilized to manage firmware across a multi-processor system
- Learn how to get started with the OpenAMP framework (topology, start-up process, API, and vendor support)
* The course version can be found in the training registration form