Xilinx & functional verification training

Taught by industry experts with real-world engineering experience

Back to

Webinar: System Protection Features of Zynq UltraScale+ MPSoCs (REL)

This webinar is free to watch. A link to the recording will be provided shortly after registration.

This webinar will highlight the different system protection features of Xilinx Zynq UltraScale+ MPSoCs, including ARM TrustZone technology, the XMPU, XPPU, and SMMU. The webinar is presented by Xilinx Authorized Training Provider Hardent.

Release date

September 13, 2017

Level

Training duration

Price

Free

Skills gained

After completing this comprehensive training, you will have the necessary skills to:

Learn about the hardware and software elements used to provide system-level protection
Discover the customizable features available within these elements
Recognize the importance of system-level protection
See how Zynq UltraScale+ MPSoCs address system protection challenges

* The course version can be found in the training registration form

Upcoming Sessions

Sep 04

SDSoC Development and Methodology (SDSoC license Included)

Sep 05–06

Embedded Design with PetaLinux Tools

Sep 05–06

Embedded Systems Software Design

Sep 05–06

C-based Design - High-Level Synthesis with the Vivado HLx Tool

Complete Course Schedule

New VDC-M (VESA Display Compression-M) IP Cores

VDC-M encoder and decoder IP cores will support the new VESA Display Compression-M standard for mobile devices requiring increased video compression levels of up to 5X.

New On-Demand SystemVerilog for Verification Training Course

Training is a valuable tool for engineering teams wanting to increase productivity, but sometimes there is simply not enough time or money available to travel to a classroom location. Hardent’s new on-demand SystemVerilog for Verification training course bridges this gap and provides students all-around flexibility in learning to use SystemVerilog technology in their verification process.

Hardent IP Portfolio Supports New Features of HDMI 2.1 Specification

VESA DSC and Reed-Solomon FEC IP cores enable HDMI controller manufacturers and IP providers to quickly implement new features of HDMI 2.1 and support higher resolution displays.

Upcoming Sessions

Sep 04

SDSoC Development and Methodology (SDSoC license Included)

Sep 05–06

Embedded Design with PetaLinux Tools

Sep 05–06

Embedded Systems Software Design

Sep 05–06

C-based Design - High-Level Synthesis with the Vivado HLx Tool

Complete Course Schedule

Your first contact at Hardent for more information about our services

Mary-Ann Conly

Training Coordinator

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

Please fill out the form to contact me:

First Name

Last Name

Title

Company

Phone

City

Country

Subject

I would like to receive electronic communications from Hardent Inc. about new training courses, advancements in electronic design and information on Hardent's services. I am aware that I can withdraw my consent at any time. For further information, please refer to our privacy policy.