Webinar: System Protection Features of Zynq UltraScale+ MPSoCs (REL)

This webinar is free to watch. A link to the recording will be provided shortly after registration.

This webinar will highlight the different system protection features of Xilinx Zynq UltraScale+ MPSoCs, including ARM TrustZone technology, the XMPU, XPPU, and SMMU. The webinar is presented by Xilinx Authorized Training Provider Hardent.

Release date

September 13, 2017

Level

Training duration

Price

Free

Skills gained

After completing this comprehensive training, you will have the necessary skills to:

Learn about the hardware and software elements used to provide system-level protection
Discover the customizable features available within these elements
Recognize the importance of system-level protection
See how Zynq UltraScale+ MPSoCs address system protection challenges

* The course version can be found in the training registration form

Upcoming Sessions

Sep 28–29

Vivado Design Suite for ISE Project Navigator Users

Sep 28

Embedded C/C++ SDSoC Development Environment and Methodology (SDSoC license included)

Oct 04–06

Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Design Suite Users

Oct 05–06

Designing with the UltraScale and UltraScale+ Architectures

Complete Course Schedule

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Upcoming Sessions

Sep 28–29

Vivado Design Suite for ISE Project Navigator Users

Sep 28

Embedded C/C++ SDSoC Development Environment and Methodology (SDSoC license included)

Oct 04–06

Vivado Design Suite Advanced XDC and Static Timing Analysis for ISE Design Suite Users

Oct 05–06

Designing with the UltraScale and UltraScale+ Architectures

Complete Course Schedule

Your first contact at Hardent for more information about our services

Ellen Kavmark

Training Manager

Linked-in

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052