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Webinar: System Protection Features of Zynq UltraScale+ MPSoCs (REL)

This webinar is free to watch. A link to the recording will be provided shortly after registration.

This webinar will highlight the different system protection features of Xilinx Zynq UltraScale+ MPSoCs, including ARM TrustZone technology, the XMPU, XPPU, and SMMU. The webinar is presented by Xilinx Authorized Training Provider Hardent.

Release date

September 13, 2017

Level

Training duration

Price

Free

Skills gained

After completing this comprehensive training, you will have the necessary skills to:

Learn about the hardware and software elements used to provide system-level protection
Discover the customizable features available within these elements
Recognize the importance of system-level protection
See how Zynq UltraScale+ MPSoCs address system protection challenges

* The course version can be found in the training registration form

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Oct 23–25

Verilog for Design

Oct 29–30

C-based Design - High-Level Synthesis with the Vivado HLx Tool

Oct 29–30

C-based Design - High-Level Synthesis with the Vivado HLx Tool

Oct 30–Nov 01

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

Complete Course Schedule

Mary-Ann Conly

Training Coordinator

HardentMontreal

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Montreal

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Canada

T +1 (514) 284-5252

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