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Webinar: System Protection Features of Zynq UltraScale+ MPSoCs (REL)

This webinar is free to watch. A link to the recording will be provided shortly after registration.

This webinar will highlight the different system protection features of Xilinx Zynq UltraScale+ MPSoCs, including ARM TrustZone technology, the XMPU, XPPU, and SMMU. The webinar is presented by Xilinx Authorized Training Provider Hardent.

Release date

September 13, 2017

Level

Training duration

Price

Free

Skills gained

After completing this comprehensive training, you will have the necessary skills to:

Learn about the hardware and software elements used to provide system-level protection
Discover the customizable features available within these elements
Recognize the importance of system-level protection
See how Zynq UltraScale+ MPSoCs address system protection challenges

* The course version can be found in the training registration form

Upcoming Sessions

Apr 25–26

Designing with the UltraScale and UltraScale+ Architectures

Apr 29–May 01

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

May 07–09

Advanced Universal Verification Methodology (UVM)

May 09–10

Advanced Timing Closure Techniques for the Vivado Design Suite

Complete Course Schedule

Hardent and Xilinx Collaborate to Deliver Complete 8K Ready DisplayPort 1.4 IP Subsystem

New IP solution combining Hardent and Xilinx IP will enable pro A/V designers to take advantage of the full DisplayPort 1.4 feature set to support resolutions up to 8K.

FPGA Design Analysis Using the Vivado Design Suite

Useful commands for FPGA design analysis in the Vivado Design Suite that will help you save time and meet your performance goals!

Hardent & Willamette HDL Named by Breker Verification Systems As PSS Training Provider For Trek5 Tool Suite

New PSS training course from Hardent and WHDL will cover unique Breker Trek5 UVM/SoC deployment and modeling capabilities.

Upcoming Sessions

Apr 25–26

Designing with the UltraScale and UltraScale+ Architectures

Apr 29–May 01

Vivado Design Suite Advanced XDC and Static Timing Analysis with Design Methodology

May 07–09

Advanced Universal Verification Methodology (UVM)

May 09–10

Advanced Timing Closure Techniques for the Vivado Design Suite

Complete Course Schedule

Mary-Ann Conly

Training Coordinator

HardentMontreal

450 rue Saint-Pierre, suite 300

Montreal

H2Y 2M9

Canada

T +1 (514) 284-5252

F +1 (514) 284-5052

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