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Xilinx & Functional Verification Training
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Webinar: System Protection Features of Zynq UltraScale+ MPSoCs (REL)

This webinar is free to watch. A link to the recording will be provided shortly after registration.

This webinar will highlight the different system protection features of Xilinx Zynq UltraScale+ MPSoCs, including ARM TrustZone technology, the XMPU, XPPU, and SMMU. The webinar is presented by Xilinx Authorized Training Provider Hardent.
Release date
September 13, 2017
Level
Training duration
Price
Free
Skills gained
After completing this comprehensive training, you will have the necessary skills to:
  • Learn about the hardware and software elements used to provide system-level protection
  • Discover the customizable features available within these elements
  • Recognize the importance of system-level protection
  • See how Zynq UltraScale+ MPSoCs address system protection challenges

* The course version can be found in the training registration form

Course Schedule

  • On-Demand
    On-Demand
    Register
Contact HardentContact me

Mary-Ann Conly

Training Coordinator

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Did you know that theĀ Canada-Ontario Job Grant program provides companies with funding for training?

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Upcoming Sessions
Feb 19–20
C-based Design - High-Level Synthesis with the Vivado HLx Tool
Register
Feb 19–21
SystemVerilog for Design
Register
Feb 21–22
Designing with the UltraScale and UltraScale+ Architectures
Register
Feb 22
SDSoC Development and Methodology (SDSoC license Included)
Register
Complete Course Schedule
Contact Hardent

Mary-Ann Conly

Training Coordinator

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