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Designing with Versal AI Engine 2

Learn about the system design flow & interfaces for data movements in the Versal AI Engine.

This course describes the system design flow and interfaces that can be used for data movements in the Versal™ AI Engine. It also demonstrates how to utilize the advanced MAC intrinsics, AI Engine library for faster development and advanced features in static data flow graph implementation such as using streams, cascade stream, buffer location constraints, run-time parameterization and APIs to update and/read run-time parameters.

The emphasis of this course is on:
  • Implementing a system-level design flow (PS + PL + AIE) and the supported simulation
  • Using an interface for data movement between the PL and AI Engine
  • Utilizing advanced MAC intrinsics to implement filters
  • Utilizing the AI Engine library for faster development
  • Applying advanced features for optimizing a system-level design

Release date

November 2020

Level

ACAP 3

Training duration

2 days

Price

USD 1800 or 18 Training Credits

Course Part Number

ACAP AIE2

Who Should Attend?

Software and hardware developers, system architects, and anyone who needs to accelerate their software applications using Xilinx devices

Prerequisites

  • Comfort with the C/C++ programming language
  • Software development flow
  • Vitis software for application acceleration development flow

Software Tools

  • Vitis unified software platform 2020.2

Hardware

  • Architecture: Xilinx Versal ACAPs

Skills gained

After completing this comprehensive training, you will have the necessary skills to:
  • Describe the system-level flow, which includes PS + PL + AIE (SW-HW-SW) designs
  • Describe the supported emulation for a system-level design
  • Describe the data movement between the PS, PL, and AI Engines
  • Describe the implementation of the AI Engine core and programmable logic
  • Implement a system-level design for Versal ACAPs with the Vitis tool flow
  • Utilize advanced MAC intrinsic syntax and application-specific intrinsics such as DDS and FFT
  • Utilize the AI Engine DSP library for faster development
  • Apply location constraints on kernels and buffers in the AI Engine array
  • Apply runtime parameters to modify application behavior
  • Debug a system-level design

Course Outline

  • Application Partitioning on Versal ACAPs - Covers what application partitioning is and how an application can be accelerated by using various compute engines in the Versal ACAP. Also describes how different models of computation (sequential, concurrent, and functional) can be mapped to the Versal ACAP. {Lecture}
  • ACAP Data Communications 1 - Describes the implementation of AI Engine cores and the programmable logic (PL). Implement the functions in AI Engine that take advantage of low power. {Lecture}
  • ACAP Data Communication 2 - Describes the programming model for the implementation of stream interfaces for the AI Engine kernels and PL kernels. Lists the stream data types that are supported by AI Engine and PL kernels. {Lecture}
  • System Design Flow - The Vitis compiler flow lets you integrate your compiled AI Engine design graph (libsdf.a) with additional kernels implemented in the PL region of the device, including HLS and RTL kernels, and link them for use on a target platform. You can call these compiled hardware functions from a host program running in the Arm® processor in the Versal device or on an external x86 processor. {Lecture, Lab}
  • Introduction to Advanced Intrinsic Functions - Describes how to implement filters using advanced intrinsics functions for various filters, such as non-symmetric FIR, symmetric FIR, half-band decimators. {Lecture}
  • Versal AI Engine DSP Library Overview - Provides an overview of the available DSP library which enables faster development and comes with ready-to-use example designs which helps with using the library and tools. {Lecture, Labs}
  • Advanced Graph Input Specifications 1 - Learn advanced features such as using initialization functions, writing directly using streams from the AI Engine, cascade stream, core location constraints, and buffer location constraints. {Lecture}
  • Advanced Graph Input Specifications 2 - Describes how to implement runtime parameterization, which can be used as adaptive feedback and switching functionality dynamically. {Lecture, Lab}
  • Versal AI Engine Application Debug and Trace - Shows to how to debug the AI Engine application running on the Linux OS and how to debug via hardware emulation that allows simulation of the application. {Lecture}

Please download the respective PDF of your course: *

  • Designing_with_Versal_AI_Engine_2_acap-aie2_2020-2_ilt_H.pdf

* The course version can be found in the training registration form

Related Course

Designing with Versal AI Engine 1

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Course Schedule

  • Jan 27–28, 2021
    Live E-Learning
    Register
  • Mar 03–04, 2021
    Live E-Learning
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  • Apr 07–08, 2021
    Live E-Learning
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Wondering Which Course to Take?

Download our learning path guide to find the right course level and topic for the next step in your career development.

Training Funding

From Xilinx training credits to government funding, there are several options available to help you cover training costs.

See our list of resources
Upcoming Sessions
Jan 19–20
Embedded Design with PetaLinux Tools
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Jan 20–21
Designing with the Versal ACAP: Programmable Logic Architecture and Methodology
Register
Jan 21
Migrating to the Vitis Embedded Software Development IDE Workshop
Register
Jan 26
Designing with the Versal ACAP: Network on Chip
Register
Complete Course Schedule
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Upcoming Sessions
Jan 19–20
Embedded Design with PetaLinux Tools
Register
Jan 20–21
Designing with the Versal ACAP: Programmable Logic Architecture and Methodology
Register
Jan 21
Migrating to the Vitis Embedded Software Development IDE Workshop
Register
Jan 26
Designing with the Versal ACAP: Network on Chip
Register
Complete Course Schedule
Contact Hardent
Your Trainer, Reg
Have a question about the course?
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We made the decision to work with Hardent as we felt confident that their strategic approach to the development process, combined with their technical expertise and training credentials, would help us to successfully reach our end goal and equip our in-house team with the electronic design knowledge to complete not just this project but other projects in the future.

Stefan Grigoras
Operations Manager
NDT Technologies Inc.
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